LVDS_TX_0_CLK
LVDS_TX_1_CLK
LVDS_TX_0_DATA
LVDS_TX_1_DATA
LGE3549
5. FRC (URSA3 – LGE7378A) block with mini-LVDS interface
I2C3_3.3V
LGE7378A (FRC)
S-Flash
(4MBIT)
DDR3
(1GBIT)
HW option
Dual Display
Control with
120Hz
(FRC)
To panel
Left mini-LVDS signals (data[10]+clk[2]
Left mini-LVDS signals (data[10]+clk[2]
Right mini-LVDS signals (data[10]+clk[2]
Right mini-LVDS signals (data[10]+clk[2]
T-CON
TIMING CONTROL SIGNALS
(H_CONV/OPT_N,POL)
GCLLK1~6
To MAX17119
(GIP module only)
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Only for training and service purposes
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