THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
TPO_DATA[6]
TPI_DATA[5]
TPI_DATA[2]
TPI_DATA[0]
TPO_DATA[7]
TPI_DATA[7]
TPI_DATA[6]
TPO_DATA[4]
TPO_DATA[5]
TPI_DATA[4]
TPI_DATA[3]
TPI_DATA[1]
TPO_DATA[0]
TPO_DATA[2]
TPO_DATA[3]
TPO_DATA[1]
R136
PWM_DIM2
100
FE_DEMOD1_TS_DATA[3]
TP161
CI_OE#
5V_DET_HDMI_1
TXA2N
EB_ADDR[4]
IC100
AT24C256C-SSHL-T
NVRAM_ATMEL
3
A2
2
A1
4
GND
1
A0
5
SDA
6
SCL
7
WP
8
VCC
FE_DEMOD1_TS_DATA[7]
TP125
EMMC_DATA[0]
C120
0.1uF
IF_FILTER
EB_ADDR[9]
USB_CTL1
TP113
TP198
R135
100
EB_ADDR[14]
TP149
BIT4
TXB1P
TP142
FE_DEMOD1_TS_SYNC
DDTS_TX
I2C_SDA1
EB_ADDR[5]
C119
0.1uF
IF_FILTER
TPI_CLK
TP343
EB_DATA[0]
TP137
R102
47
TU_SIF
EB_ADDR[5]
TP150
CI_OE#
BIT6
TXA3N
XTAL_IN
/TU_RESET1
EB_DATA[3]
CI_CE1#
TP133
R145 0
TUNER_IF_0ohm
I2C_SDA1
TP344
TPO_VAL
TPO_CLK
C103 0.1uF
TU_SIF
FE_DEMOD1_TS_CLK
TP163
I2C_SCL1
BIT7
TXB3N
EB_ADDR[8]
TPO_VAL
DDTS_RX
TP135
EB_DATA[1]
R146
0
TUNER_IF_0ohm
TP119
TP345
XTAL_OUT
EB_ADDR[10]
C110
1000pF
OPT
CI_RESET
IC101
LGE6322(MSD93F2G, w/oT2S2 : M2)
EAN64207702
NON-MCP
PWM0
A25
PWM1
B26
PWM2
B25
PWM3
C24
PWM_PM
D7
SAR0
E6
SAR1
E5
SAR2
F5
SAR3
F6
SAR4
G5
PM_SPI_CK
B2
PM_SPI_DI
A2
PM_SPI_DO
B1
NC_13
H8
GPIO_PM[6]/(SPI-CZ1N)
C1
GPIO_PM[10]/(SPI-CZ2N)
C2
PM_SPI_HOLDN(GPIO)
A3
PM_SPI_WPN/(GPIO)
C3
DDCA_CK
D5
DDCA_DA
D6
DDCR_CK
J21
DDCR_DA
H21
UART_TX2
H22
UART_RX2
H23
GPIO7/TX1
E22
GPIO8/RX1
F21
GPIO11/TX3
E20
GPIO12/RX3
F20
PCM2_WAIT_N/TX4
AB6
PCM2_IRQA_N
M23
PCM2_CE_N
M22
NC_14
AC6
GPIO_PM[0]
J5
GPIO_PM[1](PM_UART)
E8
GPIO_PM[2]
M4
GPIO_PM[3]
J6
GPIO_PM[4]
N4
GPIO_PM[5](PM_UART)
F8
GPIO_PM[7]
K5
GPIO_PM[8]
K6
GPIO_PM[9]
L6
GPIO_PM[11]/(PM_UART)
C4
GPIO_PM[12](PM_UART)
B4
GPIO_PM[15]
B3
GPIO17/SCKM0
K21
GPIO18/SDAM0
L22
GPIO15/SCKM2
K22
GPIO14/SDAM2
L21
TCON5/SCKM4
J22
TCON4/SDAM4
K23
R_ODD[7]/LVB0N
G25
R_ODD[6]/LVB0P
G24
R_ODD[5]/LVB1N
H25
R_ODD[4]/LVB1P
H24
R_ODD[3]/LVB2N
J25
R_ODD[2]/LVB2P
J26
R_ODD[1]/LVBCLKN
J24
R_ODD[0]/LVBCLKP
K26
G_ODD[7]/LVB3N
K25
G_ODD[6]/LVB3P
K24
G_ODD[5]/LVB4N
L25
G_ODD[4]/LVB4P
L24
G_ODD[3]/LVA0N
M25
G_ODD[2]/LVA0P
M26
G_ODD[1]/LVA1N
M24
G_ODD[0]/LVA1P
N26
B_ODD[7]/LVA2N
N25
B_ODD[6]/LVA2P
N24
B_ODD[5]/LVACLKN
P25
B_ODD[4]/LVACLKP
P24
B_ODD[3]/LVA3N
R25
B_ODD[2]/LVA3P
R26
B_ODD[1]/LVA4N
R24
B_ODD[0]/LVA4P
T26
SPI1_DI
F25
SPI1_CK
F26
GPIO6
L23
GPIO9
N23
GPIO10
N22
VSYNC_LIKE
F24
TS2_D[1]
AA23
TS2_D[3]
Y23
TS2_D[2]
AA22
LINEIN_L3
Y2
LINEIN_R3
Y4
TS2_D[4]
Y22
TS2_D[5]
W23
TS2_D[6]
W22
TS2_D[7]
W21
NC_15
AD2
NC_16
AD1
IRIN
C5
VID0
F7
VID1
E7
XTAL_IN
AE1
XTAL_OUT
AF2
GND_1
M11
GND_2
M7
NC_17
J7
RESET
D8
EB_ADDR[12]
BIT5
TXACLKP
EMMC_DATA[1]
CI_CD#
JK101
12507WS-04L
DEBUG
1
2
3
4
5
TP106
EB_DATA[1]
AGP
TPI_DATA[0-7]
TP346
TPO_SYNC
EB_ADDR[7]
R103 47
TU_SIF
EB_DATA[6]
IC101
LGE6322(MSD93F2G, w/oT2S2 : M2)
NON-MCP
PCM_D[0]
T25
PCM_D[1]
AB26
PCM_D[2]
Y24
PCM_D[3]
P21
PCM_D[4]
R22
PCM_D[5]
AA24
PCM_D[6]
T21
PCM_D[7]
V21
PCM_A[0]
V26
PCM_A[1]
V23
PCM_A[2]
N21
PCM_A[3]
U23
PCM_A[4]
W26
PCM_A[5]
AA25
PCM_A[6]
U22
PCM_A[7]
V25
PCM_A[8]
V22
PCM_A[9]
V24
PCM_A[10]
P22
PCM_A[11]
U21
PCM_A[12]
W25
PCM_A[13]
Y25
PCM_A[14]
AB24
PCM_IRQA_N
T23
PCM_OE_N
R21
PCM_IORD_N
T22
PCM_CE_N
AB25
PCM_WE_N
AA26
PCM_CD_N
U25
PCM_RESET
T24
PCM_REG_N
P23
PCM_IOWR_N
U24
PCM_WAIT_N
W24
EMMC_IO[8](EMMC_DS)(NAND_ALE)
AD26
EMMC_IO[10](EMMC_CLK)(NAND_RBZ)
AC25
EMMC_IO[9](EMMC_CMD)
AC24
EMMC_IO[11](EMMC_RSTN)
AD25
EMMC_IO[0](EMMC_D0)(NAND_CEZ)
AF24
EMMC_IO[1](EMMC_D1)(NAND_WPZ)
AE24
EMMC_IO[2](EMMC_D2)(NAND_CLE)
AF25
EMMC_IO[3]/(EMMC_D3)(NAND_DQS)
AD23
EMMC_IO[4](EMMC_D4)(NAND_REZ)
AF23
EMMC_IO[5](EMMC_D5)(NAND_CE1Z)
AE23
EMMC_IO[6](EMMC_D6)(NAND_WEZ)
AE26
EMMC_IO[7](EMMC_D7)
AE25
TS1_D[0]
AA21
TS1_D[1]
W20
TS1_D[2]
AB20
TS1_D[3]
AB19
TS1_D[4]
W19
TS1_D[5]
AB21
TS1_D[6]
AA19
TS1_D[7]
AA20
TS1_CLK
Y20
TS1_VLD
Y21
TS1_SYNC
Y19
TS0_D[0]
AF20
TS0_D[1]
AC21
TS0_D[2]
AE21
TS0_D[3]
AF21
TS0_D[4]
AC19
TS0_D[5]
AD20
TS0_D[6]
AE20
TS0_D[7]
AE19
TS0_CLK
AD19
TS0_VLD
AE22
TS0_SYNC
AD21
TS2_SYNC
AB22
TS2_CLK
AC22
TS2_VLD
AC23
TS2_D[0]
AB23
NC_1
AC3
NC_2
AB2
NC_3
AB3
NC_4
AA1
NC_5
AC2
NC_6
AC4
VIFP
AF4
VIFM
AE4
SIFP
AF5
SIFM
AE5
IFAGC
AD4
TGPIO0
AB4
TGPIO1
AD5
TGPIO2/SCKM1
AE3
TGPIO3/SDAM1
AD3
NC_7
P10
NC_8
N10
NC_9
N11
NC_10
P11
NC_11
R10
NC_12
R11
EB_ADDR[1]
EMMC_STRB
TXB2P
EB_ADDR[11]
EB_ADDR[4]
+3.3V_SB
I2C_SCL2
EB_ADDR[1]
+3.3V_NORMAL
EB_DATA[4]
TP347
+3.3V_TUNER
TP143
C102 0.1uF
TU_SIF
TP147
IC101-*1
LGE6321(MSD93F2GW, w/ T2S2 : M2)
MCP
PCM_D[0]
T25
PCM_D[1]
AB26
PCM_D[2]
Y24
PCM_D[3]
P21
PCM_D[4]
R22
PCM_D[5]
AA24
PCM_D[6]
T21
PCM_D[7]
V21
PCM_A[0]
V26
PCM_A[1]
V23
PCM_A[2]
N21
PCM_A[3]
U23
PCM_A[4]
W26
PCM_A[5]
AA25
PCM_A[6]
U22
PCM_A[7]
V25
PCM_A[8]
V22
PCM_A[9]
V24
PCM_A[10]
P22
PCM_A[11]
U21
PCM_A[12]
W25
PCM_A[13]
Y25
PCM_A[14]
AB24
PCM_IRQA_N
T23
PCM_OE_N
R21
PCM_IORD_N
T22
PCM_CE_N
AB25
PCM_WE_N
AA26
PCM_CD_N
U25
PCM_RESET
T24
PCM_REG_N
P23
PCM_IOWR_N
U24
PCM_WAIT_N
W24
EMMC_IO[8](EMMC_DS)(NAND_ALE)
AD26
EMMC_IO[10](EMMC_CLK)(NAND_RBZ)
AC25
EMMC_IO[9](EMMC_CMD)
AC24
EMMC_IO[11](EMMC_RSTN)
AD25
EMMC_IO[0](EMMC_D0)(NAND_CEZ)
AF24
EMMC_IO[1](EMMC_D1)(NAND_WPZ)
AE24
EMMC_IO[2](EMMC_D2)(NAND_CLE)
AF25
EMMC_IO[3]/(EMMC_D3)(NAND_DQS)
AD23
EMMC_IO[4](EMMC_D4)(NAND_REZ)
AF23
EMMC_IO[5](EMMC_D5)(NAND_CE1Z)
AE23
EMMC_IO[6](EMMC_D6)(NAND_WEZ)
AE26
EMMC_IO[7](EMMC_D7)
AE25
TS1_D[0]
AA21
TS1_D[1]
W20
TS1_D[2]
AB20
TS1_D[3]
AB19
TS1_D[4]
W19
TS1_D[5]
AB21
TS1_D[6]
AA19
TS1_D[7]
AA20
TS1_CLK
Y20
TS1_VLD
Y21
TS1_SYNC
Y19
TS0_D[0]
AF20
TS0_D[1]
AC21
TS0_D[2]
AE21
TS0_D[3]
AF21
TS0_D[4]
AC19
TS0_D[5]
AD20
TS0_D[6]
AE20
TS0_D[7]
AE19
TS0_CLK
AD19
TS0_VLD
AE22
TS0_SYNC
AD21
TS2_SYNC
AB22
TS2_CLK
AC22
TS2_VLD
AC23
TS2_D[0]
AB23
NC_1
AC3
NC_2
AB2
NC_3
AB3
NC_4
AA1
NC_5
AC2
NC_6
AC4
VIFP
AF4
VIFM
AE4
SIFP
AF5
SIFM
AE5
IFAGC
AD4
TGPIO0
AB4
TGPIO1
AD5
TGPIO2/SCKM1
AE3
TGPIO3/SDAM1
AD3
NC_7
P10
NC_8
N10
NC_9
N11
NC_10
P11
NC_11
R10
NC_12
R11
TP112
TXB1N
I_P_SoC
TP131
I2C_SDA2
R148 10K
OPT
TP128
MCP_SCL
EMMC_DATA[6]
TP145
TP121
CI_WAIT#
IC101-*1
LGE6321(MSD93F2GW, w/ T2S2 : M2)
EAN64207701
MCP
PWM0
A25
PWM1
B26
PWM2
B25
PWM3
C24
PWM_PM
D7
SAR0
E6
SAR1
E5
SAR2
F5
SAR3
F6
SAR4
G5
PM_SPI_CK
B2
PM_SPI_DI
A2
PM_SPI_DO
B1
NC_13
H8
GPIO_PM[6]/(SPI-CZ1N)
C1
GPIO_PM[10]/(SPI-CZ2N)
C2
PM_SPI_HOLDN(GPIO)
A3
PM_SPI_WPN/(GPIO)
C3
DDCA_CK
D5
DDCA_DA
D6
DDCR_CK
J21
DDCR_DA
H21
UART_TX2
H22
UART_RX2
H23
GPIO7/TX1
E22
GPIO8/RX1
F21
GPIO11/TX3
E20
GPIO12/RX3
F20
PCM2_WAIT_N/TX4
AB6
PCM2_IRQA_N
M23
PCM2_CE_N
M22
NC_14
AC6
GPIO_PM[0]
J5
GPIO_PM[1](PM_UART)
E8
GPIO_PM[2]
M4
GPIO_PM[3]
J6
GPIO_PM[4]
N4
GPIO_PM[5](PM_UART)
F8
GPIO_PM[7]
K5
GPIO_PM[8]
K6
GPIO_PM[9]
L6
GPIO_PM[11]/(PM_UART)
C4
GPIO_PM[12](PM_UART)
B4
GPIO_PM[15]
B3
GPIO17/SCKM0
K21
GPIO18/SDAM0
L22
GPIO15/SCKM2
K22
GPIO14/SDAM2
L21
TCON5/SCKM4
J22
TCON4/SDAM4
K23
R_ODD[7]/LVB0N
G25
R_ODD[6]/LVB0P
G24
R_ODD[5]/LVB1N
H25
R_ODD[4]/LVB1P
H24
R_ODD[3]/LVB2N
J25
R_ODD[2]/LVB2P
J26
R_ODD[1]/LVBCLKN
J24
R_ODD[0]/LVBCLKP
K26
G_ODD[7]/LVB3N
K25
G_ODD[6]/LVB3P
K24
G_ODD[5]/LVB4N
L25
G_ODD[4]/LVB4P
L24
G_ODD[3]/LVA0N
M25
G_ODD[2]/LVA0P
M26
G_ODD[1]/LVA1N
M24
G_ODD[0]/LVA1P
N26
B_ODD[7]/LVA2N
N25
B_ODD[6]/LVA2P
N24
B_ODD[5]/LVACLKN
P25
B_ODD[4]/LVACLKP
P24
B_ODD[3]/LVA3N
R25
B_ODD[2]/LVA3P
R26
B_ODD[1]/LVA4N
R24
B_ODD[0]/LVA4P
T26
SPI1_DI
F25
SPI1_CK
F26
GPIO6
L23
GPIO9
N23
GPIO10
N22
VSYNC_LIKE
F24
TS2_D[1]
AA23
TS2_D[3]
Y23
TS2_D[2]
AA22
LINEIN_L3
Y2
LINEIN_R3
Y4
TS2_D[4]
Y22
TS2_D[5]
W23
TS2_D[6]
W22
TS2_D[7]
W21
NC_15
AD2
NC_16
AD1
IRIN
C5
VID0
F7
VID1
E7
XTAL_IN
AE1
XTAL_OUT
AF2
GND_1
M11
GND_2
M7
NC_17
J7
RESET
D8
VDD33
TXA2P
I_N_SoC
I2C_SCL3
TP123
R149 10K
OPT
EB_ADDR[0]
TP118
AR104
3.3K
T2/S2
EB_ADDR[13]
IF_N
FE_DEMOD1_TS_DATA[5]
EMMC_DATA[7]
TU_SIF
EB_DATA[7]
TXB3P
+3.3V_NORMAL
EMMC_DATA[4]
R150
0
OPT
TXB0P
Q_P_SoC
CI_WAIT#
EB_DATA[5]
I2C_SCL1
EMMC_DATA[5]
EB_DATA[0]
TP144
PWM_DIM2
TP148
TP141
TXA1N
+3.3V_NORMAL
FE_DEMOD1_TS_DATA[0]
R138
10K
NON_EU
TXA1P
Q_N_SoC
CI_REG#
JK100
12507WS-04L
DEBUG
1
2
3
4
5
TP199
EB_ADDR[10]
JK102
12507WS-04L
T2/S2
1
2
3
4
5
TP110
IF_AGC
+3.3V_NORMAL
I2C_SDA3
PCM_5V_CTL
EMMC_CMD
I2C_SDA2
CI_IORD#
WOL_WAKE_UP_SOC
TXA0P
LNB_TX
EB_ADDR[3]
DDCA_CK
CI_CD#
C112
0.1uF
MCP_SDA
TP108
R144
10K
IF_FILTER
TP146
TPI_VAL
R152 33
I2C_SDA1
I2C_SCL2
EB_DATA[7]
TXA0N
IF_AGC_S_SOC
TPI_VAL
DDCA_DA
CI_REG#
R115
1.8K
MCP_SCL
TPI_SYNC
TP115
EB_DATA[3]
R105
10K
OPT
TPO_DATA[0-7]
I2C_SDA3
+3.3V_NORMAL
EB_ADDR[13]
TP120
TXBCLKN
IF_AGC_S_SOC
TP130
DDCA_CK
EB_DATA[5]
R116
1.8K
MCP_SDA
CI_IREQ#
AMP_RESET_N
C123
33pF
IF_FILTER_CAP
EB_DATA[2]
TP140
R106
10K
OPT
TP116
I2C_SCL3
+3.3V_NORMAL
EB_DATA[4]
EB_ADDR[3]
LNB_TX
TP117
DDCA_DA
TP109
IC100-*1
BR24G256FJ-3
NVRAM_ROHM
3
A2
2
A1
4
GND
1
A0
5
SDA
6
SCL
7
WP
8
VCC
R117
300
1%
OPT
TPO_SYNC
TP127
C122
33pF
IF_FILTER_CAP
TP111
EB_ADDR[2]
EB_DATA[6]
I2C_SDA4
+3.3V_NORMAL
CI_RESET
FE_DEMOD1_TS_DATA[1]
C124
0.022uF
16V
IF_FILTER
I_P_SoC
CI_IOWR#
DDTS_TX
PCM_5V_CTL
FE_DEMOD1_TS_DATA[2]
EB_DATA[2]
C118
0.1uF
IF_FILTER
TP126
CI_IOWR#
+3.3V_SB
TPI_SYNC
I2C_SCL4
R140
0
XTAL_IN
VID_CTRL
I_N_SoC
CI_IREQ#
DDTS_RX
TXB0N
TPI_CLK
TP138
TPO_DATA[0-7]
AR101
33
EMMC_DATA[2]
/USB_OCD1
R141
0
OPT
SOC_TX
R153 33
Q_P_SoC
EB_ADDR[2]
M_RFModule_RESET
TXB2N
FE_DEMOD1_TS_VAL
EMMC_CLK
R147
0
IF_FILTER
PWM_DIM
EB_ADDR[6]
AR102
3.3K
EB_ADDR[6]
AV_CVBS_DET
TPI_DATA[0-7]
CI_IORD#
R101
10K
T2/S2
Q_N_SoC
EB_ADDR[0]
COMP2_DET
TXACLKN
XTAL_OUT
EMMC_RST
FE_DEMOD1_TS_DATA[4]
IF_P
EB_ADDR[12]
CI_WE#
AR103
3.3K
EB_ADDR[9]
USB_CTL2
CI_WE#
EB_ADDR[14]
R104
10K
OPT
TP160
TP134
SOC_RESET
TXA3P
R137
1M
TP114
EB_ADDR[7]
CI_CE1#
+3.3V_SB
RETENTION_DISABLE
SOC_RX
/USB_OCD2
I2C_SCL1
EMMC_DATA[3]
TP132
TP162
TP139
5V_DET_HDMI_3
TXBCLKP
X100
24MHz
SUNNY ELECTRONICS CORPORATION
3225
4
GND_2
1
X-TAL_1
2
GND_1
3
X-TAL_2
EB_ADDR[11]
C121
100pF
OPT
TPO_CLK
EB_ADDR[8]
INSTANT_BOOT
TP136
5V_DET_HDMI_2
TP129
FE_DEMOD1_TS_DATA[6]
I2C_SDA4
TP164
I2C_SCL4
TP165
C100-*1
8pF
50V
0CZZB00024A
8pF
C101-*1
8pF
50V
8pF
TP166
5V_DET_HDMI_2
/USB_OCD2
TP167
USB_CTL2
TP168
R145-*1
100
TUNER_IF_100ohm
R146-*1
100
TUNER_IF_100ohm
L102
BLM15PX121SN1
IF_FILTER
PWM_DIM2
TP1014
HP_LOUT_SOC
TP1012
HP_ROUT_SOC
HP_DET
TP1013
TP1011
TXB0P
TP1007
TXB1P
TP1006
TP1003
TP1001
TXB3N
TP1010
TP1008
TXB3P
TP1004
TP1002
TP1005
TXB0N
TP1009
TXBCLKN
TXBCLKP
TXB1N
TXB2P
TXB2N
M_RFModule_RESET
TP1015
EYE_SDA
TP1016
EYE_SCL
TP1017
MIU0_STR_PD
MIU1_STR_PD
MIU0_STR_PD
MIU1_STR_PD
TP1030
TP1031
C101
10pF
50V
10pF
C100
10pF
50V
10pF
2015.10.02
1
MAIN1
16Y_M2
FOR BRAZIL Energy Regulation
need to ADD SILK
"LJ6 CHASSIS"
P/NO
MCP : EAN64207701 (MSD93F2GW)
NON MCP : EAN64207702 (MSD93F2G)
SATELLITE
SATELLITE
MCP for T2/S2
NVRAM
I2C_1 : AMP, L/D, NVM, TCON
I2C_2 : TUNER
I2C_3 : MICOM
I2C_4 : S/Demod,T2/Demod, LNB ==> only for LNB - Satellite Model
Write Protection
- Low : Normal Operation
- High : Write Protection
I2C
Close to MSTAR
DDTS_Debug
Mstart Debug
MCP Debug
X-TAL
SATELLITE - LNB only
10pF Option
FOR LH57 HD MODEL
FOR LH57 EU MODEL
Copyright © 2016 LG Electronics Inc. All rights reserved.
Only for training and service purposes
To Next Page
Loading...
