LG 65UF9500 - Page 75

4. URSA9 Block Diagram
URSA9
LGE7411
I2C_SCL1/SDA1
1Gb x 4 (1866)
DDR3
16x4
Vx1 8Lane 41P
Vx1 8Lane 51P
H15
4K@60p Vx1 8 Lane Video
1080p / 2160p Vx1 4 Lane OSD
[GPIO[14]]
URSA9_CONNECT
[GPIO140]
[GPIO[16]]
Vx1_LOCKn_O/V
[TX_LOCKN]
H1
5
LOCKn_IN/ HTPDn_IN
[VX1_LOCKN]
[VX1_HTDPN]
Panel
3840x2160@120
p
Serial
Flash(4MB)
SPI_CZ
SPI_D
O
SPI_C
K
SPI_DI
XIN_URSA
XO_URSA
URSA_RESET_MICOM
(MICOM PORT #24)
[RESET]
[I2CS_SDA/SCL]
I2CS_SDA/SCL
UART2_RX
UART2_TX
(URSA9_PQ_DEBUG)
GPIO[1]/[0]
DIM5/GPIO[37]
DIM6/GPIO[38]
DIM7/GPIO[39]
URSA_BIT0/1/2
[VBY1_RXM[0]~[7]
[VBY1_RXP[0]~[7]
[VBY1_RXM[8]~[11]
[VBY1_RXP[8]~[11]
[TXDAN0/P0~N7/P7_L]
[TXDBN0/P0~N7/P7_L]
X-tal
24MHz
BIT[2/1/0]
UD_V x 1 Lane
수
0/0/0
4K@120P(16Lanes)
0/0/1
4K@60P(8Lanes)
0/1/0
5K@120P(20Lanes)
0/1/1
OLED ULTRA HD
1/0/0
FHD@120 (4Lane)
1/0/1
FHD@60 (2Lane)
1/1/0
Reserved
1/1/1
Reserved
[C4TX_0N/P~7N/P]
[C4TX_8N/P~11N/P]
MICOM
/FRC_FLASH_WP
[SCL2/GPIO78]
[SDA2/GPIO77]
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Only for training and service purposes
LGE Internal Use Only