3. TECHNICAL BRIEF
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(1) Receiver Part
The Aero II transceiver uses a digital low-IF receiver architecture that allows for the on-chip integration of
the channel selection filters, eliminating the external RF image reject filters, and the IF SAW filter required in
conventional superheterodyne architectures. Compared with direct-conversion architectures, the digital low-
IF architecture has a much greater degree of immunity to dc offsets that can arise from RF local oscillator
(RFLO) self-mixing, second-order distortion of blockers (AM suppression), and device 1/f noise.
The digital low-IF receiver's immunity to dc offsets has the benefit of expanding part selection and improving
manufacturing. At the front end, the common-mode balance requirements on the input SAW filters are
relaxed, and the PCB board design is simplified. At the radio's opposite end, the BBIC is one of the
handset's largest BOM contributors. It is not uncommon for a direct conversion solution to be compatible
only with a BBIC from the same supplier in order to address the complex dc offset issues. However, since
the Aero II transceiver has no requirement for BBIC support of complex dc offset compensation, it is able to
interface to all of the industry leading baseband ICs.
The receive (RX) section integrates four differential input low noise amplifiers (LNAs) supporting the GSM
850 (869-894 MHz), E-GSM 900 (925-960 MHz), DCS 1800 (1805-1880 MHz), and PCS 1900 (1930-1990
MHz) bands. The LNA inputs are matched to 150 or 200 balanced-output SAW filters through external LC
matching networks. See “AN150: Aero II Transceiver PCB Design Guide” for implementation details. The
active LNA input is automatically selected by the ARFCN[9:0] bits and the BANDIND bit in Register 21h. If
performing LNA swapping, the LNASWAP bit in Register 05h is also needed. Please refer to section 4.1.1
for details. The LNA gain is controlled with the LNAG bit in Register 20h.
A quadrature image-reject mixer downconverts the RF signal to a low intermediate frequency (IF). The
mixer output is amplified with an analog programmable gain amplifier (PGA) that is controlled with the
AGAIN[2:0] bits in Register 20h. The quadrature IF signal is digitized with high resolution analog-
todigital converters (ADCs).
Figure. 3-2 SI4210 RECEIVER PART
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