3. TECHNICAL BRIEF
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CPU INTERFACE
CPU interface is an 8-bit parallel.
4 control signal(/wr,/rd,/cs,A0 pin), 8 data bit(D0 to D7), and 1 interrupt pin(/IRQ), totaling 13 pins are
connected to the external CPU. This block controls the writing and reading of data by the input polarity
of control signal
INTERFACE REGISTER
This registeris able to access directly ffrom the external CPU. There are 2 bytes spaces. The
Intermediate register can be accessed through the interface register.
INTERMEDIATE REGISTER
This register is accessed through the Interface register.
It is composed to access a latter control register and ROM/SRAM through Intermediate register.
This register is called “Intermediate register” since this exists in the middle of the interface register and
the Control register.
In the Intermediate register, there are some registers to control various functions.
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