LG LG-D618 - Page 145

5. BLOCK DIAGRAM
- 145 -
Copyright © 2014 LG Electronics. Inc. All right reserved.
Only for training and service purposes
LGE Internal Use Only
VSW_S1
VDD CORE
VDD_USB_COR
VSW_S2
VDD_APC
V
SW
_
S5
V
DD
_
MODEM
_
01
+1V15_MSM_CP_CORE
+1V05_MSM_AP_CORE
+1V15_VSW_S5
4.7” qHD
(960X540)
+1V8_LCD_IO
VREG_L8
H/S
DETECTOR
+VPWR
_
__
VREG_L1
VDD_RF1
VDD_A1
VREG_L2
VDD_P1
VREG_L3
VDD_MEM
VDD_PLL1
+1V225_WTR_RF1
+1V225_MSM_A1
+1V2_MSM_P1
+1V15_MSM_MEM
WTR2605
+2V05_WTR_RF2
VDD_RF2
VREG_L9
VREG_L10
+1V8_WTR_RF3_IO
Motor
+VPWR
V
COIN
MSM8226
VDD_EBI0_CDC
VREG_L6 MODE
FORCED_USB_BOOT/GPIO_113
+1V8_MSM_IO
+1V8_EAR_DETECT_VDD
VREG_L7
+1V9_MSM_A2
VDD_A2
FEMID
VIO
HCPA_APT_A
CPM7700
VIO
VREG_L14
+2V75_VREG_L14
+3V075_MSM_USB_3P3
VREG L20
VDD USB 3P3
PM8226
(PMIC)
MSM8226
(1.2GHz Quad
Cortex-A7)
CPM7700
LM3263
VDD_1P8
VREG
_
L20
VDD
_
USB
_
3P3
VDD_P2
+2V95_MSM_P2
VREG_L21
+2V95_USIM1
VREG_L22
VDD_P5
+2V95_USIM2
VDD_P6
VREG_L23
Hall IC
+1V8_HALL_VDD
VDD
VOUT_LVS1
+VPWR
VSW_S3
VDD_GR1
+1V35_VSW_S3
VSW_S4
+2V1_PM_GR3
e
ry
VBAT
VBAT
+VPWR
Char
g
in
g
VDD_S1
VDD_S2
VDD_S3
VDD_S4
VDD_S5
VDD_WLED
VDD_GR5
VDD_GR6
VDD_GR7
VDD_GR2
VDD_GR3
VDD_GR4
+2V1_PM_GR4
VREG_L4
VDD_MIPI_CSI
VDD_MIPI_DSI_1P2
V
RE
G
L
5
+1V2_CODEC_CORE
+1V8_MSM_P3, P4, P7, P8
V
DD
_
P3, P4, P7, P8
+2V95_eMMC_VCC
VCC1
VREG L17
USB Con.
Batt
e
USB_IN
VBUS_USB_IN (5V)
VCHG
OVP
OVP_OUT
+5V0_VREG_BHARGER
gg
IC
WCD9302
(
Codec)
VDD_BUCK
+2V1_CODEC_BUCK
VDD_DIG
VREG
_
L5
VDD TX RX
+1V8_CODEC_IO
_, , ,
VDD_DDR_CORE_1P8
+1V8_MSM_DDR_CORE_1P8
eMMC v4.5
8GB
+1V8_eMMC_VCCQ
WCN3620
VREG_L15
VCC1
VREG
_
L17
VREG_L23
+1V3_WCN_RF
VDD_WLAN
VOUT_LVS1
+VPWR
Flash LED
+
VPWR
(
Codec)
+1V2_MAIN_CAM_DVDD
8M Cam
(AF)
VDD
_
TX
_
RX
VDD_IO
+1V8_CODEC_IO
IRRC circuits
+1V8_IRRC_TR
`
WCN3620
(BT/WLAN/FM)
+1V8_WCN_IO
+2V8_MAIN_CAM_AF
+1V8_MAIN_CAM_DVDD
+
VPWR
[LGD618] Power