2.5.2 WRITE DATA TO PSG SEQUENCE
The “Write to PSG” sequence, which would normally follow immedi-
ately after an address sequence, requires four principal microstates:
(1) send NACT (inactive); (2) put data on bus; (3) send DWS (write to
PSG); (4) send NACT (inactive).
2.5.3 READ DATA FROM PSG SEQUENCE
As with the “Write to PSG” sequence, the ”Read from PSG” sequence
would also normally follow immediately after an address sequence.
The four principal microstates of the read sequence are: (1) send
NACT (inactive); (2) send DTB (read from PSG); (3) read data on bus;
(4) send NACT (inactive).
2.5.4 WRITE TO/READ FROM l/O PORT SEQUENCE
Since the two I/O Ports (A and B) each have an 8-bit register assigned
as a data store, writing to or reading from either port is identical to
writing or reading to any other register. Hence, the state sequences
are exactly-the same as described in the preceding paragraphs.
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