3.4 The amplitudes of the signals generated by each of the three D/A
Amplitude
Converters (one each for Channels A, B, and C) is determined by the
contents of the lower 5 bits (B4--BO) of registers R10, Rl11, and R12 as
control
illustrated in the following:
Amplitude Control
(Registers R10, R11, R12)
Register #
Channel
R10
A
Rll
B
R12
C
amplitude
4-bit “fixed”
“Mode”
amplitude Level.
The amplitude “mode” (bit M) selects either fixed level amplitude
(M=0) or variable level amplitude (M=1). It follows then that bits L3--
L0, defining the value of a “fixed” level amplitude, are only active
when M=0. When fixed level amplitude isselected, it is “fixed” only in
the sense that the amplitude level is under the direct control of the
system processor (via bits D3--D0). Varying the amplitude when in
this “fixed” amplitude mode requires in each instance the direct
intervention of the system processor via an address latch/write data
sequence to modify the D3--D0 data.
When M=1 (select “variable” level amplitudes), the amplitudeof each
channel is determined by the envelope pattern as defined by the
Envelope Generator’s 4-bit output E3 E2 E1 EO.
The amplitude “mode” (bit M) can also be thought of as an “envelope
enable” bit; i.e., when M=0 the envelope is not used, and when M=1
the envelope is enabled. (A full description of the Envelope Gener-
ator function follows in Section 3.5).
To Next Page
Loading...