4.4
The ROM or PROM shown connected to the PSG in Fig. 17 illustrates
External
an option for providing additional data information for processor
support. The two I/O registers within the PSG are used in this case to
Memory
address the memory via I/O Port A (8 Bits) and read data from the
memory via I/O Port B (8 Bits).
Access A
n
example of the bus control sequence to address and read an
external memory connected to I/O ports A and B would be as follows
(Assume Port A addresses and Port B reads):
Bus codes
Bus Control
BDIR BC2 BC1 Explanation of Bus Data (DA7--DA0)
Latch address
1 1
1
00000111: Latch R7 to program I/O Ports
Write to PSG
1 1
0 01000000: Set B7. B6 to 0, 1 respectively
Latch address
1 1
1
00001110: Latch R16 to address memory
Write to PSG
1 1
0 00000001: Address data to memory
Latch address
1 1
1
00001111: Latch R17 to read memory
Read from PSG 0 1
1
XXXXXXXX: Memory data contained in R17
NOTE: BC2 in the above Bus Codes may be permanently tied to +5V thus
requiring only two bus control lines for all control operations (refer to
Section 2.3 for a complete explanation).
Also, RAM or EAROM may be used in place of the ROM or PROM
shown by altering the program to use PORT B as an I/O. Port B then
will be able to write data as an output and read data as an input.
Fig. 17 EXTERNAL MEMORY ACCESS
I
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