Microchip Technology ay-3-8910 - Interfacing to the M6800

4.8 An M6800 microprocessor can be interfaced with an AY-3-8910/8912
Interfacing
through the addition of an M6820 PIA chip. The I/O portsdesignated
as PA0 to PA7 are used as the 8 bit bus lines and I/O ports PB0 to PB2
to the M6800
are used as the bus control lines. The software routines shown are
used to control the latch address, write data, and read data functions
for the AY-3-8910/8912.
4.8.1 LATCH ADDRESS ROUTINE
;AT ENTRY, B HAS ADDRESS VALUE
LATCH CLRA
STAA 8005 ;GET D DIR A
LDAA #FF
STAA 8004 ;OUTPUTS
LDAA #4
STAA 8005 ;GET PERIPHERAL A
STAB 8004 ;FORM ADDR
STAA 8006
CLRA
STAA 8006 ;LATCH ADDRESS
RTS ;RETURN
4.8.2 WRITE DATA ROUTINE
;AT ENTRY, B HAD DATA VALUE
WRITE STAB 8004 ;FORM DATA
LDAA #6 ;DWS
STAA 8006
CLRA
STAA 8006 ;WRITE DATA
RTS ;RETURN
I
4.8.3 READ DATA ROUTINE
;AFTER READ, B HAS READ DATA
READ STA A 8005 ;GET D DIR
STA A 8004 ;INPUTS
LDAA #4
STA A 8005 ;GET PERIPHERAL
DECA
STA A 8006 ;READ MODE
LDA B 8004 ;READ DATA
CLRA
STA A 8006 ;REMOVE READ MODE
RTS ;RETURN