4.9
Interfacing
to the 8080
The sample S100 bus design provides for reading and writing the
PSG using only an 8080 “IN” or “OUT” instruction to the proper
address. Another feature of the design is the provision for multiple
PSG devices to be connected to a single bus. The system described is
presently running two PSG’s,
one
to each of
two
stereo channels.
S100 Bus
As can be seen from the read and write routines in the illustrative
program, the program overhead necessary to communicate with the
PSG is minimal.
4.9.1 LATCH ADDRESS ROUTINE
PORTADDR EQU 80H ;ADDRESS TRANSFER PORT ADDRESS
PORTDATA EQU 81H ;DATA TRANSFER PORT ADDRESS
THIS ROUTINE WILL TRANSFER THE CONTENTS OF
;8080 REGISTER C TO THE PSG ADDRESS REGISTER
PSGBAR
MOV A,C ;GET C IN A FOR OUT
OUT
PORTBAR ;SEND TO ADDRESS PORT
RET
4.9.2 WRITE DATA ROUTINE
ROUTINETO WRITE THE CONTENTS OF 8080 REGISTER B
;TO THE PSG REGISTER SPECIFIED BY 8080 REGISTER C
PSGWRITE CALL PSGBAR ;GET ADDRESS LATCHED
MOV A.B, ;GET VALUE IN A FOR TRANSFER
RET PORTDATA ;PUT TO PSG REGISTER
4.9.3 READ DATA ROUTINE
ROUTlNE TO READ THE PSG REGISTER SPECIFIED
;BY THE 8080 REGISTER C AND RETURN THE DATA
;IN 8080 REGISTER B
PSGREAD CALL PSGBAR
IN
PORTDATA ;GET REGISTER DATA
MOV B,A GET IN TRANSFER REGISTER
RET
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