21
Basic
Functional
Blocks
(cont.)
Conditioning of the Register Address Latch/Decoder and the Bidi-
rectional Buffers to recognize the bus function required (inactive,
latch address, write data, or read data) is accomplished by the Bus
Control Decode block.
The function of each of the 16 PSG registers and the data flow of each
register’s contents are shown in context in Fig. 2 and explained in
detail in Section 3, “Operation”. For reference purposes, the Register
Array details are reproduced in Fig. 3.
2.1.2 SOUND GENERATING BLOCKS
The basic blocks in the PSG which produce the programmed sounds
include:
Tone Generators
Noise Generator
Mixers
Amplitude Control
Envelope Generator
D/A Converters
produce the basic square wave tone frequen-
cies for each channel (A,B,C)
produces a frequency modulated pseudo
random pulse width square wave output.
combine the outputs of the Tone Generators
and the Noise Generator. One for each chan-
nel (A,B,C).
provides the D/A Converters with either a
fixed or variable amplitude pattern. The fixed
amplitude is under‘ direct ‘CPU control; the
variable amplitude is accomplished by using
the output of the Envelope Generator.
produces an envelope pattern which can be
used to amplitude modulate the output of
each Mixer.
the three D/A Converters each produce up to
a 16 level output signal as determined by the
Amplitude Control.
2.1.3 I/O PORTS
Two additional blocks are shown in the PSG Block Diagram which
have nothing directly to do with the production of sound-these are
the two I/O Ports (A and B). Since virtually all uses of microproces-
sor-based sound. would require interfacing between the outside
world and the processor, this facility has been included in the PSG.
Data to/from the CPU bus may be read/written to either of two 8-bit
I/O Ports without affecting any other function of the PSG. The I/O
Ports are TTL-compatible and are provided with internal pull-ups on
each pin. Both Ports are available on the AY-3-8910; only I/O Port A is
available on the AY-3-8912.
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