Mitsubishi Electric MELSEC iQ-F Series - Page 43

4 FUNCTIONS
4.2 Cyclic Transmission
41
4
Output data hold/clear operation during CPU STOP
The following figure shows the devices where the setting of "Output Hold/Clear Setting during CPU STOP" is enabled when
the FX5 CPU module on the sending side changes from RUN to STOP.
At unicast mode
: When the link refresh source is set to a source other than Y, data is held or cleared according to the parameter setting. When the link refresh source is set
to Y, data is cleared regardless of the parameter setting.
: Data is held regardless of the parameter setting.
RX
RY
RWr
RWw
No.1
No.3
No.3
No.2
No.1
No.2
No.1
No.2
No.3
No.1
No.2
No.3
No.0
RX
RY
RWr
RWw
No.1
No.1
No.1
No.1
No.1
RX
RY
RWr
RWw
No.2
No.2
No.2
No.2
No.2
RX
RY
RWr
RWw
No.3
No.3
No.3
No.3
No.3