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Mitsubishi Electric MELSEC iQ-R Series - Page 1405

Mitsubishi Electric MELSEC iQ-R Series
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12 MULTIPLE CPU DEDICATED INSTRUCTIONS
12.1 Another CPU Module Access Instructions
1403
12
Number of available blocks
Another CPU module access instructions use the system area in minimum units of blocks, each consisting of 16 words.
The following table lists the numbers of blocks available for another CPU module access instructions.
The following figure shows how blocks are used in a multiple CPU system consisting of three CPU modules.
Maximum number of data points that can be read or written
The maximum number of data points that can be read or written by an instruction depends on the number of CPU modules in
a multiple CPU system configuration.
Number of blocks used by instructions
The number of blocks used by instructions depends on the number of read/write data points. The following table lists the
numbers of blocks used by instructions.
Number of CPU modules Maximum number of blocks
2 599
3 299
4 199
Number of CPU
modules
Maximum number of data points that can be read Maximum number of data points that can be written
2 modules 8192 point 8192 point
3 modules 4096 point 4096 point
4 modules 2048 point 2048 point
Reading/
writing
Number of blocks Example
Read Number of blocks used by instructions = (21 + number of
read data points)16
When the number of read data points is 100
Number of blocks used by instructions = (21 + 100)16 = 7 [blocks]
Write Number of blocks used by instructions = (19 + number of
write data points)16
When the number of write data points is 100
Number of blocks used by instructions = (19 + 100)16 = 7 [blocks]
Send area
(to CPU No.2)
299
blocks
299
blocks
Receive area
(from CPU No.1)
Send area
(to CPU No.3)
Receive area
(from CPU No.1)
299
blocks
Receive area
(from CPU No.2)
299
blocks
Send area
(to CPU No.1)
Send area
(to CPU No.3)
Receive area
(from CPU No.2)
299
blocks
Receive area
(from CPU No.3)
299
blocks
Send area
(to CPU No.1)
Receive area
(from CPU No.3)
Send area
(to CPU No.2)
299
blocks
299
blocks
299
blocks
299
blocks
299
blocks
299
blocks
CPU No.1 system area CPU No.2 system area CPU No.3 system area
Data send area from CPU No.1 to CPU No.2 and No.3
Data send area from CPU No.2 to CPU No.1 and No.3
Data send area from CPU No.3 to CPU No.1 and No.2

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