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12 MULTIPLE CPU DEDICATED INSTRUCTIONS
12.1 Another CPU Module Access Instructions
Simultaneous execution of another CPU module access Instructions
Another CPU module access instructions can be executed simultaneously within the range of the following expression.
If executing another CPU module access instruction causes the number of blocks used by the CPU module access
instructions to exceed the total number of blocks in the system area, the instruction is not executed (no processing) in the
relevant scan and is executed in the next scan.
Note, however, that this instruction is completed with an error if the number of empty block in the system area is less than the
value specified in SD796 to SD799 (maximum number of blocks for multiple CPU dedicated instructions) when the instruction
is executed.
The table below shows whether another CPU module access instruction can be executed when the number of empty blocks
in the system area is less than the number of blocks used by another CPU module access instructions or the value set in
SD796 to SD799.
*1 Number of blocks used by another CPU module access instructions
*2 Number of empty blocks in the system area
*3 Value set in SD796 to SD799
Interlock applied when another CPU module access instructions are used
Special relay SM796 to SM799 is used for interlocking among another CPU module access instructions.
When executing multiple another CPU module access instructions concurrently, use SM796 to SM799 for interlocking among
these instructions.
When using SM796 to SM799, specify the maximum numbers of blocks of the instructions used by individual
CPU modules in SD796 to SD799. For example, when the maximum number of blocks used by another CPU
module access instructions executed for CPU module No. 3 is 5, specify 5 in SD798.
When the number of blocks specified in any of SD796 to SD799 is exceeded, the relevant special relay
(SM796 to SM799) turns on.
Precautions
• Execute the D(P).DDWR, M(P).DDWR, D(P).DDRD, or M(P).DDRD instruction while the read/write target CPU module is
on. If the instruction is executed while the target CPU is not on, the instruction performs no processing.
• After the D(P).DDWR, M(P).DDWR, D(P).DDRD, or M(P).DDRD instruction is executed, do not change the device range
specified in the setting data before the completion device is turned on; otherwise, the completion status and completion
device data can no longer be stored in the system.
• SB/SW and SM/SD include the system information area. When writing data with the D(P)DDWR or M(P).DDWR instruction,
be careful not to overwrite the system information area.
• If the number of blocks used by the instruction to be executed is greater than the value set in SD796 to SD799, the
instruction may not be executed (terminated abnormally) even if it is interlocked with SD796 to SD799.
• Set SD796 to SD799 before executing the instruction for the corresponding CPU module. (It is recommended to set them in
the first scan after the CPU module runs.)
Conditions under which another CPU module access instructions can be executed simultaneously
[Number of blocks available for each CPU module][total number of blocks used by concurrently executed instructions]
Size relationship between the value set in
SD
*3
and number of empty blocks
*2
Size relationship between the number of blocks used by instruction
*1
and number of
empty blocks
Number of blocks used by instruction
and number of empty blocks
Number of blocks used by instruction >
number of empty blocks
Value set in SD number of empty blocks Executed Not executed (non-processing)
Value set in SD > number of empty blocks Completed with an error
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