Mitsubishi Electric MELSEC iQ-RJ71C24-R2 - Page 501

APPENDICES APPENDIX
Appendix 3 Buffer Memory
499
A
128
(80H)
For
programmable
controller CPU
information clear
Programmable controller CPU information clear
request
0: No request
4C43H: Requested
0RW Page 455 How to
Clear Programmable
Controller CPU
Information
129 to 143
(81H to 8FH)
Use prohibited System area 
144
(90H)
304
(130H)
For designation
of mode
switching
Switching mode No. designation (0001H to
0007H, 0009H, 00FFH)
0000H: Match the setting in MELSOFT.
0001H: MC protocol (Format 1)
0002H: MC protocol (Format 2)
0003H: MC protocol (Format 3)
0004H: MC protocol (Format 4)
0005H: MC protocol (Format 5)
0006H: Nonprocedural protocol
0007H: Bidirectional protocol
0009H: Predefined protocol
00FFH: MELSOFT connection
0 RW Page 380 I/O Signals
for Handshake with
CPU Module and
Buffer Memory
145
(91H)
305
(131H)
For designation
of mode
switching
Transmission specifications after switching
designation
Designates transmission specifications after
switching when b15 of this area is 1 (ON).
• Operation setting (b0)
0: Independent 1: Interlink
• Data bit (b1)
0: 7 bits 1: 8 bits
• Parity bit (b2)
0: None 1: Yes
• Odd/even parity (b3)
0: Odd 1: Even
• Stop bit (b4)
0: 1 bit 1: 2 bits
• Sum check code (b5)
0: None 1: Yes
• Online change (b6)
0: Disable 1: Enable
• Setting change (b7)
0: Disable 1: Enable
• Communication speed (b8 to b11)
1200 bps to 230400 bps
• For system (b12 to b14)
All 0
• Transmission specifications direction after
switching (b15)
0: Match settings in MELSOFT
1: Match settings in this area
0
146
(92H)
306
(132H)
Signal
specification
RS and DTR signal status designation
0: OFF 1: ON
RS (RTS) signal (b0)
ER (DTR) signal (b2)
For system (b1), (b3) to (b15)
5H MELSEC iQ-R Serial
Communication
Module User's
Manual (Startup)
Address
Dec (Hex)
Purpose Name Defaul
t value
Protocol Reference
CH1 CH2 MC Non Bi Pd