Mitsubishi Electric MELSEC iQ-RJ71C24-R4 - Page 289

15 DATA COMMUNICATIONS USING USER FRAMES
15.2 Data Reception
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■Combination without the start frame (Timing patterns for data reception start and data
reception complete (read))
Pattern No. 2-A 1) Pattern No. 2-A 2)
Last frame Last frame
Target device
Arbitrary data Arbitrary data
CPU module
For the received
data count
Pattern No. 2-A 3) Pattern No. 2-A 4)
Complete code
Last frame
Complete code
Last frame
Target device
Arbitrary data Arbitrary data
CPU module
For the received
data count
Arbitrary data Arbitrary data
Pattern No. 2-B
: Reception start timing
: Receive complete timing (read timing)
Last frame
Target device
CPU module