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3 SPECIFICATIONS
3.2 Performance Specifications
3.2 Performance Specifications
The following table lists the performance specifications of the flexible high-speed I/O control module.
Item Specifications
Differential DC
Number of input points 12 points (common for 5VDC/24VDC/differential)
Number of output points 6 points 8 points (5 to 24VDC, 0.1A/point)
Number of interrupts 8 points
Input response time 1μs or less
Output response time 1μs or less
Pulse input speed Max. 8Mpps (2MHz) Max. 200kpps (200kHz)
Pulse output speed Max. 8Mpps (2MHz) Max. 200kpps (200kHz)
Main block
*1
External input
block
Logic Select Inverted, not inverted
Filter Time General-purpose
input:
0μs, 10μs, 50μs, 0.1ms, 0.2ms, 0.4ms, 0.6ms, 1ms, 5ms
Pulse input: 10kpps, 100kpps, 200kpps, 500kpps, 1000kpps, 2000kpps,
4000kpps, 8000kpps
Initial State Low, High
Y device terminal Outputs the ON/OFF states of General command 0 to General command F (Y10 to
Y1F) as signals.
OUT terminal Outputs the same signal as the one to be output from the external output block.
Parallel
encoder block
Input Data Type Pure binary, Gray code, BCD
Data Length 1 bit to 12 bits
SSI encoder
block
Input Data Type Pure binary, Gray code
Data Length 1 bit to 32 bits
Multi function
counter block
Terminal Input terminal, latch input terminal, event input terminal, output terminal, event output
terminal, cam switch output terminal
Input signal event detection block Combination of rise, fall, Low, and High
Latch event detection block Rise, fall
Counter timer
block
Type Addition, subtraction, linear counter mode, ring counter mode, addition mode, preset
counter function, latch counter function, internal clock function
Internal clock 25ns, 50ns, 0.1μs, 1μs, 10μs, 100μs, 1ms
Counting range 32-bit signed binary (-2147483648 to 2147483647)
32-bit unsigned binary (0 to 4294967295)
16-bit signed binary (-32768 to 32767)
16-bit unsigned binary (0 to 65535)
Compare block Compare Value Same as the counting range
Compare Mode 16-bit counter: =, >, <, ≥, ≤, <>
32-bit counter: =, >, <, ≥, ≤, <>
Cam switch
block
Refreshing
cycle
0.1μs
Number of
steps
Up to 16 steps
Set/reset block Uses the signal input to the Set terminal as a trigger to output the High fixed signal.
Uses the signal input to the Reset terminal as a trigger to output the Low fixed signal.
Logical
operation block
Logical operation type AND, OR, XOR
External output
block
Logic Select Inverted, not inverted
Delay Time None, 12.5ns × (1 to 64), 25ns × (1 to 64), 50ns × (1 to 64), 0.1μs × (1 to 64), 1μs × (1
to 64), 10μs × (1 to 64), 100μs × (1 to 64), 1ms
× (
1 to 64)
Error-time Output Mode OFF, ON, HOLD
SI device terminal Interrupt to a CPU module
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