Mitsubishi Electric MELSEC-Q Series - Page 203

7 REPLACEMENT OF PROGRAM
7 - 16
*1 Note that the buffer memory address between Q series and AnS series may differ.
Left rotation of 32-bit data
DROL DROL  Section 7.7.8
DROLP DROLP  Section 7.7.8
Right rotation of 32-bit data
DROR DROR  Section 7.7.8
DRORP DRORP  Section 7.7.8
1-word shift to left of n-word data
DSFL DSFL 
DSFLP DSFLP 
1-word shift to right of n-word data
DSFR DSFR 
DSFRP DSFRP 
32 bit data checks
DSUM DSUM  Section 7.7.8
DSUMP DSUMP  Section 7.7.8
2-word data write to the intelligent/special function
module
DTO DTO

*1
DTOP DTOP

*1
Timing pulse generation DUTY DUTY 
32-bit data conversion
DXCH DXCH 
DXCHP DXCHP 
32-bit data non-exclusive logical sum operations
DXNR DXNR 
DXNRP DXNRP 
32-bit exclusive logical sum operations
DXOR DXOR 
DXORP DXORP 
Interrupt enable instruction EI EI 
Link refresh enable EI EI 
256  8-bit encode
ENCO ENCO 
ENCOP ENCOP 
Sequence program termination END END 
Main routine program termination FEND FEND 
Reading oldest data from tables
FIFR FIFR 
FIFRP FIFRP 
Writing data to the data table
FIFW FIFW 
FIFWP FIFWP 
Identical 16-bit data block transfers
FMOV FMOV 
FMOVP FMOVP 
FOR to NEXT instruction FOR FOR 
1-word data read from the intelligent/
special function module
FROM FROM

*1
FROMP FROMP

*1
16-bit BIN data increment
INC INC 
INCP INCP 
Return from interrupt programs IRET IRET 
Pointer branch instruction JMP JMP 
Operation start LD LD 
BIN 16-bit data comparison
LD< LD< 
LD<= LD<= 
LD<> LD<> 
LD= LD= 
LD> LD> 
LD>= LD>= 
BIN 32-bit data comparison
LDD< LDD< 
LDD<= LDD<= 
LDD<> LDD<> 
LDD= LDD= 
LDD> LDD> 
LDD>= LDD>= 
Operation start LDI LDI 
ASCII code display instruction LED OUT SM1255  Section 7.2.3 (3)
Description
AnSCPU QnUCPU
Reference
Instruction name Instruction name Conversion