13
COMMUNICATIONS BETWEEN CPU MODULES
13.2 Interrupt from Another CPU
13 - 7
9
DEVICE DESCRIPTION
10
MULTIPLE CPU SYSTEM
OVERVIEW
11
MULTIPLE CPU SYSTEM
CONFIGURATION
12
CONCEPT OF MULTIPLE
CPU SYSTEM
13
COMMUNICATIONS
BETWEEN CPU
MODULES
14
PARAMETERS ADDED
FOR MULTIPLE CPU
SYSTEMS
15
STARTING A MULTIPLE
CPU SYSTEM
16
TROUBLESHOOTING
(4) Dedicated instructions
The following shows programmable controller CPU dedicated instructions used for
interrupt from a programmable controller CPU (another CPU).
: Available, : Partially available, : N/A
* 1 For the Basic model QCPU, High Performance model QCPU, and Universal model QCPU, index
modification is available.
* 2 For the Basic model QCPU and Universal model QCPU, index modification is available.
* 3 Only when both of (D1) and (D2) are omitted, they can be actually omitted.
* 4 Local devices cannot be used.
Table 13.3 Devices available for S(P).GINT and D(P).GINT instructions
Setting
data
Available devices
Internal device
(System, user)
File register
R, ZR
Link direct device
J\
Intelligent
function module
U\G
Index
register, Zn
Constant
K, H
Others
Bit Word Bit Word Bit Word
(n1)
*1
(n2)
*2
(D1)
*3 *4 *4
(D2)
*3 *4 *4
Figure 13.5 S(P).GINT instruction
Figure 13.6 D(P).GINT instruction
[Instruction symbol]
SP.GINT
S.GINT
[Execution condition]
SP.GINT (n1) (n2)
S.GINT (n1) (n2)
Command
Command
[Instruction symbol]
DP.GINT
[Execution condition]
DP.GINT (n1) (n2)
DP.GINT (D1) (D2)
Command
Command
D.GINT
(n1) (n2)
D.GINT (n1) (n2)
D.GINT (D1) (D2)(n1) (n2)
Command
Command