13
COMMUNICATIONS BETWEEN CPU MODULES
13.2 Interrupt from Another CPU
13 - 9
9
DEVICE DESCRIPTION
10
MULTIPLE CPU SYSTEM
OVERVIEW
11
MULTIPLE CPU SYSTEM
CONFIGURATION
12
CONCEPT OF MULTIPLE
CPU SYSTEM
13
COMMUNICATIONS
BETWEEN CPU
MODULES
14
PARAMETERS ADDED
FOR MULTIPLE CPU
SYSTEMS
15
STARTING A MULTIPLE
CPU SYSTEM
16
TROUBLESHOOTING
(d) Operation timing
(e) Error details
In any of the following cases, an operation error occurs, the error flag (SM0) of the
programmable controller CPU is set to ON, and an error code is stored in SD0.
* 1 0000H (Normal)
Figure 13.7 Operation timing of the S(P).GINT instruction
Table 13.6 Error codes related to S(P).GINT and D(P).GINT instructions
Error code
*1
Cause Action
2110
CPU No. of a reserved ("Empty" setting) or non-mounted
CPU is specified for the target CPU start I/O No. 16 (n1).
Check and
correct the
sequence
program.
2114
The originating CPU is specified for the target CPU start I/O
No. 16 (n1).
2117
A module that does not support the S(P).GINT and
D(P).GINT instructions is specified for the target CPU start I/
O No. 16 (n1).
4100
Any of 0 to 3DF
H, or 3E4H is specified for the target CPU
start I/O No. 16 (n1).
Sequence program
SM391 (S(P).GINT instruction
execution completed flag)
t
END END END END
S(P).GINT instruction executed
OFF
S(P).GINT instruction executed
S(P).GINT instruction not executed
C Controller module interrupt
routine (interrupt program)
C Controller module user
program
Interrupt issued
ON
ON
User program resumed
OFF
Interrupt event in waiting status by user program
QBF_Wait Event function
executed
Interrupt event notified
*1
Interrupt routine (interrupt
program) executed
Interrupt routine (interrupt program)
in waiting status
*1 Interrupt event notified after the interrupt routine (interrupt program) ends.
Interrupt routine (interrupt program) in waiting status
S(P). GINT instruction