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Mitsubishi Electric Q12DCCPU-V - Page 411

Mitsubishi Electric Q12DCCPU-V
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13
COMMUNICATIONS BETWEEN CPU MODULES
13.3 Data Communications Using CPU Shared Memory
13 - 13
9
DEVICE DESCRIPTION
10
MULTIPLE CPU SYSTEM
OVERVIEW
11
MULTIPLE CPU SYSTEM
CONFIGURATION
12
CONCEPT OF MULTIPLE
CPU SYSTEM
13
COMMUNICATIONS
BETWEEN CPU
MODULES
14
PARAMETERS ADDED
FOR MULTIPLE CPU
SYSTEMS
15
STARTING A MULTIPLE
CPU SYSTEM
16
TROUBLESHOOTING
POINT
The CPU shared memory is accessible only when the number of CPUs is set to 2
or more in <<Multiple CPU settings>> of C Controller setting utility.
If the CPU shared memory is accessed without setting two or more CPU modules,
CPU No. error (return value: -28662) is detected.
Remark
For the bus interface functions, refer to the following.
C Controller Module User's Manual (Utility Operation, Programming)

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