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Mitsubishi Electric Q12DCCPU-V - Page 413

Mitsubishi Electric Q12DCCPU-V
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13
COMMUNICATIONS BETWEEN CPU MODULES
13.3 Data Communications Using CPU Shared Memory
13.3.1 CPU shared memory structure
13 - 15
9
DEVICE DESCRIPTION
10
MULTIPLE CPU SYSTEM
OVERVIEW
11
MULTIPLE CPU SYSTEM
CONFIGURATION
12
CONCEPT OF MULTIPLE
CPU SYSTEM
13
COMMUNICATIONS
BETWEEN CPU
MODULES
14
PARAMETERS ADDED
FOR MULTIPLE CPU
SYSTEMS
15
STARTING A MULTIPLE
CPU SYSTEM
16
TROUBLESHOOTING
POINT
For the Q06CCPU-V(-B), communication using the multiple CPU high speed
transmission area is not available.
Use the QCPU standard area.
Table 13.9 CPU shared memory structure
Area name Description
QCPU standard
area
Host CPU operation
information area
Error details or operation status of the host CPU (C Controller module)
are stored in this area. ( Table 13.10)
System area This area is used by the system.
Auto refresh area
This area data are automatically refreshed into devices of the
programmable controller CPU or Motion CPU, based on the auto refresh
settings.
The area size varies depending on the parameter settings.
User setting area
This area can be used at user's discretion.
The area size varies depending on the parameter settings for the Auto
refresh area.
Use prohibited This area cannot be used.
Multiple CPU high speed transmission area
This area is used for the multiple CPU high speed transmission.
The auto refresh area or user setting area can be set with a parameter.

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