Mitsubishi Electric Q12DCCPU-V - Precautions for Data Communications Using Auto Refresh; Example of Parameter Setting for Interlock Program

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COMMUNICATIONS BETWEEN CPU MODULES
13.3 Data Communications Using CPU Shared Memory
13.3.2 Data communications using auto refresh
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DEVICE DESCRIPTION
10
MULTIPLE CPU SYSTEM OVERVIEW
11
MULTIPLE CPU SYSTEM CONFIGURATION
12
CONCEPT OF MULTIPLE CPU SYSTEM
13
COMMUNICATIONS BETWEEN CPU MODULES
14
PARAMETERS ADDED FOR MULTIPLE CPU SYSTEMS
15
STARTING A MULTIPLE CPU SYSTEM
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TROUBLESHOOTING
(3) Precautions for data communications using auto refresh
Depending on the timing of writing data to the host CPU's auto refresh area or reading
data from another CPU, old and new data may be mixed in the area for each CPU.
Therefore, configure an interlock program for auto refresh so that data of another
CPU will not be used when old and new data are mixed.
(a) Interlock program example
Figure 13.15 shows an interlock program example for sending data from CPU
No.1 (programmable controller CPU) to CPU No.2 (C Controller module).
The parameter setting in Table 13.11 uses the following interlock devices.
• M0 as an interlock device (Data set completion bit) of CPU No.1
• M32 as an interlock device (Data processing completion bit) of CPU No.2
Table 13.11 Example of parameter setting for interlock program
Auto refresh setting for CPU No.1
Direction
Auto refresh setting for CPU No.2
CPU
No.
Transfer
No.
CPU specific send
range
Device
setting
CPU
No.
Transfer
No.
CPU specific send
range
Points Start End Start End Points Start End
No.1
Transfer 1 2 0 1 M0 M31
No.1
Transfer 1 2 0 1
Transfer 2 10 2 11 D0 D9 Transfer 2 10 2 11
No.2 Transfer 1 2 0 1 M32 M63 No.2 Transfer 1 2 0 1