Mitsubishi Electric Q12DCCPU-V - Addresses of the Multiple CPU High Speed Transmission Area

13
COMMUNICATIONS BETWEEN CPU MODULES
13.3 Data Communications Using CPU Shared Memory
13.3.4 Data communications without using auto refresh
13 - 41
9
DEVICE DESCRIPTION
10
MULTIPLE CPU SYSTEM OVERVIEW
11
MULTIPLE CPU SYSTEM CONFIGURATION
12
CONCEPT OF MULTIPLE CPU SYSTEM
13
COMMUNICATIONS BETWEEN CPU MODULES
14
PARAMETERS ADDED FOR MULTIPLE CPU SYSTEMS
15
STARTING A MULTIPLE CPU SYSTEM
16
TROUBLESHOOTING
(b) Addresses of the multiple CPU high speed transmission area
Figure 13.28 shows the addresses in the multiple CPU high speed transmission
area.
The last address of each CPU's send area shown in Figure 13.28 varies
depending on the points set in "CPU specific send range" in the "Multiple CPU
settings" tab.
* 1 This figure indicates the addresses when specifying the User setting area for each CPU by the
multiple CPU device (Specified by the Universal model QCPU)
For each area of the Multiple CPU high speed transmission area, refer to the
following.
Page 13-24, Section 13.3.3
Figure 13.28 Memory configuration of the Multiple CPU high speed transmission area
Multiple CPU high speed
transmission area
CPU No.1 send area
User setting area
CPU No.2 send area
CPU No.3 send area
CPU No.4 send area
Auto refresh area
U3E0\G10000 *1
U3E1\G10000 *1
U3E2\G10000 *1
U3E3\G10000 *1