3 - 24 3 - 24
MELSEC-Q
3 SPECIFICATIONS
3.4.3 Buffer memory assignment (Q68DAVN/Q68DAV)
This section describes the assignment of the Q68DAVN/Q68DAV buffer memory.
POINT
Do not write data from System area or sequence program to the buffer memory
area where writing is disabled. Doing so may cause malfunction.
Table 3.9 Buffer memory assignment (Q68DAVN/Q68DAV) (1/2)
Address
Description Default
1
Read/write
2
Reference
section
Hexadecimal Decimal
0H 0 D/A conversion enable/disable FFH R/W Section 3.4.5
1H 1 CH1 Digital value 0 R/W
Section 3.4.6
2H 2 CH2 Digital value 0 R/W
3H 3 CH3 Digital value 0 R/W
4H 4 CH4 Digital value 0 R/W
5H 5 CH5 Digital value 0 R/W
6H 6 CH6 Digital value 0 R/W
7H 7 CH7 Digital value 0 R/W
8H 8 CH8 Digital value 0 R/W
9H 9
System area — — —
AH 10
BH 11 CH1 Set value check code 0 R
Section 3.4.7
CH 12 CH2 Set value check code 0 R
DH 13 CH3 Set value check code 0 R
EH 14 CH4 Set value check code 0 R
FH 15 CH5 Set value check code 0 R
10H 16 CH6 Set value check code 0 R
11H 17 CH7 Set value check code 0 R
12H 18 CH8 Set value check code 0 R
13H 19 Error code 0 R/W Section 3.4.8
14H 20 Setting range (CH1 to CH4) 2222H R
Section 3.4.9
15H 21 Setting range (CH5 to CH8) 2222H R
16H 22
Offset/gain setting mode
Offset specification
0 R/W
Section 3.4.10
17H 23
Offset/gain setting mode
Gain specification
0 R/W
18H 24 Offset/gain adjustment value specification 0 R/W Section 3.4.11
1 This is the initial value set after the power is turned on or the programmable controller CPU is reset.
2 Indicates whether reading from and writing to a sequence program are enabled.
R : Reading enabled W : Writing enabled