Mitsubishi Electric RD62P2E - Appendix 3 Buffer Memory Areas; List of Buffer Memory Addresses

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APPENDICES
Appendix 3 Buffer Memory Areas
Appendix 3 Buffer Memory Areas
List of buffer memory addresses
The following table lists the buffer memory addresses of the high-speed counter module. For details on the buffer memory
addresses, refer to the following.
Page 62 Details of buffer memory addresses
Do not write any data to the system area or the area whose data type is monitor in the buffer memory. Writing
any data in those areas may cause a malfunction.
Address
Decimal (hexadecimal)
Name Default value Data type Auto refresh
CH1 CH2
0 (0H) 32 (20H) CH Preset value setting (L) 0 Setting 
1 (1H) 33 (21H) CH Preset value setting (H) 0 Setting 
2 (2H) 34 (22H) CH Present value (L) 0 Monitor 
3 (3H) 35 (23H) CH Present value (H) 0 Monitor 
4 (4H) 36 (24H) CH Coincidence output point No.1 setting (L) 0 Setting 
5 (5H) 37 (25H) CH Coincidence output point No.1 setting (H) 0 Setting 
6 (6H) 38 (26H) CH Coincidence output point No.2 setting (L) 0 Setting 
7 (7H) 39 (27H) CH Coincidence output point No.2 setting (H) 0 Setting 
8 (8H) 40 (28H) CH Overflow detection 0 Monitor 
9 (9H) 41 (29H) CH Counter function selection setting 0 Setting 
10 (0AH) 42 (2AH) CH Sampling/cycle time setting 0 Setting 
11 (0BH) 43 (2BH) CH Sampling/cycle counter flag 0 Monitor 
12 (0CH) 44 (2CH) CH Latch count value (L) 0 Monitor 
13 (0DH) 45 (2DH) CH Latch count value (H) 0 Monitor 
14 (0EH) 46 (2EH) CH Sampling count value (L) 0 Monitor 
15 (0FH) 47 (2FH) CH Sampling count value (H) 0 Monitor 
16 (10H) 48 (30H) CH Cycle pulse count previous value (L) 0 Monitor 
17 (11H) 49 (31H) CH Cycle pulse count previous value (H) 0 Monitor 
18 (12H) 50 (32H) CH Cycle pulse count current value (L) 0 Monitor 
19 (13H) 51 (33H) CH Cycle pulse count current value (H) 0 Monitor 
20 (14H) 52 (34H) CH Ring counter lower limit value setting (L) 0 Setting 
21 (15H) 53 (35H) CH Ring counter lower limit value setting (H) 0 Setting 
22 (16H) 54 (36H) CH Ring counter upper limit value setting (L) 0 Setting 
23 (17H) 55 (37H) CH Ring counter upper limit value setting (H) 0 Setting 
24 (18H) 56 (38H) CH Cycle pulse count difference value (LL) 0 Monitor 
25 (19H) 57 (39H) CH C
ycle pulse count difference value (LH) 0 Monitor 
26 (1AH) 58 (3AH) CH Cycle pulse count difference value (HL) 0 Monitor 
27 (1BH) 59 (3BH) CH Cycle pulse count difference value (HH) 0 Monitor 
28 (1CH) 60 (3CH) CH Counter function update flag 0 Monitor 
29 (1DH) 61 (3DH) CH Signal monitor Depends on external
signal status
Monitor 
30 (1EH) 62 (3EH) CH Synchronization latch count value (L) 0 Monitor 
31 (1FH) 63 (3FH) CH Synchronization latch count value (H) 0 Monitor 
64 to 255 (40H to FFH) System area 
256 (100H) 272 (110H) CH PWM output cycle time setting (L) FFFFH Control 
257 (101H) 273 (111H) CH PWM output cycle time setting (H) 7FFFH Control 
258 (102H) 274 (112H) CH PWM output ON time setting 1 (L) 0 Control 
259 (103H) 275 (113H) CH PWM output ON time setting 1 (H) 0 Control 
260 (104H) 276 (114H) CH PWM output ON time setting 2 (L) 0 Control 