Registers
http://www.motorola.com/computer/literature 2-39
2
PCI Command/ Status Registers
IOSP IO Space Enable. If set, the Raven will respond to PCI I/O accesses
when appropriate. If cleared, the Raven will not respond to PCI I/O space
accesses.
MEMSP Memory Space Enable. If set, the Raven will respond to PCI
memory space accesses when appropriate. If cleared, the Raven will not
respond to PCI memory space accesses.
MSTR Bus Master Enable. If set, the Raven may act as a master on PCI.
If cleared, the Raven may not act as a PCI master.
PERR Parity Error Response. If set, the Raven will check parity on all
PCI transfers. If cleared, the Raven will ignore any parity errors that it
detects and continue normal operation.
SERR System Error Enable. This bit enables the SERR* output pin. If
clear, the Raven will never drive SERR*. If set, the Raven will drive
SERR* active when a system error is detected.
FAST Fast Back-to-Back Capable. This bit indicates that the Raven is
capable of accepting fast back-to-back transactions with different targets.
Offset $04
Bit 3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9876543210
Name PSTAT PCOMM
RCVPE
SIGSE
RCVMA
RCVTA
SIGTA
SELTIM1
SELTIM0
DPAR
FAST
SERR
PERR
MSTR
MEMSP
IOSP
Operation
R/C
R/C
R/C
R/C
R/C
R
R
R/C
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R/W
R
R/W
R
R
R
R/W
R/W
R/W
Reset
0
0
0
0
0
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
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