http://www.motorola.com/computer/literature IN-5
I
N
D
E
X
P
P1 and P2 connectors 4-19, 5-6
parameters, ENV command 3-11
parity DRAM emulations 1-16
part numbers, SIM 1-10
Petra ASIC
Abort switch interrupt 4-12
control of BBRAM and clock 4-11
control of Flash access time 4-11
IP bus Strobe* signal 1-13, 2-7, 4-16
IP2 function 1-8, 4-15
LAN coprocessor support 4-17
local bus timeout function 4-18
logic duplicated in VMEchip2 4-7
MC2 function 1-15, 1-17, 2-5, 4-13
MCECC function 1-21
memory controller emulations 4-7
programmable tick timers 4-17
SCSI controller support 4-17
SRAM control 4-9
watchdog timer 4-18
pin assignments, connector 5-1
port number(s), debugger command 3-5
power requirements A-1
powering up the board 2-1
power-save mode 4-9
preparing the board 1-1
processor
bus structure 4-6
cache memory 4-6
location monitors 1-27
programmable tick timers 4-17
Q
QIC-02 streaming tape drive D-4
R
regulatory compliance A-4
related specifications E-3
relative humidity A-1
remote control/status connector (J6) 4-20,
5-3
RESET switch 4-20
resetting the system 2-1, 2-12
RF emissions, minimizing 1-24, A-4
ROMboot process 2-10
S
safety procedures 1-4
SCC (serial communications controller) 2-8
SCSI
common command set (CCS) devices
D-2, D-4
controller (53C710) 4-17
direct access devices D-2
interface 4-17
sequential access devices D-2
termination 4-17
terminator configuration 4-17
terminator power 1-27
SD command 2-14
SDRAM (synchronous DRAM)
options 4-7
sequential access devices D-4
serial
communication parameters 2-4
communications controller (SCC) 2-8
communications interface 1-28, 4-12
communications interface (port 1
signals) 5-6
communications interface (port 2
signals) 5-5
connectors 4-19
interfaces and transition boards 4-15
serial interface modules (SIMs)
connector 5-4
considerations for transition modules
4-15
installation 1-11
model numbers 4-13
part numbers 1-10
removal 1-10
selection 1-9
serial port 2, MVME712M 4-13, 4-14
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