Motorola MVME2400 Series - PCI Bus Latency; Table 3-3. PCI Originated Latency Matrix

Block Diagram
http://www.motorola.com/computer/literature 3-7
3
PCI Bus Latency
The following tables list the latency of PCI originated transactions and the
bandwidth of originated transactions for five different clock ratios: 5:2,
3:2, 3:1, 2:1, and 1:1. The MVME2400 uses a 3:1 clock ratio:
Table 3-3. PCI Originated Latency Matrix
Transaction
32-bit PCI 64-bit PCI
Clock
Ratio
Beat
1
Beat
2
Beat
3
Beat
4
Total
Beat
1
Beat
2
Beat
3
Beat
4
Total
Burst Read9111129111125:2
Burst Write3111631116
Single Read 9 - - - 9 9 - - - 9
Single Write3---33---3
Burst Read121111512111153:2
Burst Write3111631116
Single Read12---1212---12
Single Write3---33---3
Burst Read9111129111123:1
Burst Write3111631116
Single Read 9 - - - 9 - - - - -
Single Write3---3-----
Burst Read111111411111142:1
Burst Write3111631116
Single Read11---11-----
Single Write3---3-----
Burst Read161111916111191:1
Burst Write3111631116
Single Read16---16-----
Single Write3---3-----