Motorola MVME2400 Series - Assumptions; Clock Ratios and Operating Frequencies; Ppc60 X Originated; Table 3-7. Clock Ratios and Operating Frequencies

Block Diagram
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3
Assumptions
Certain assumptions have been made with regard to MVME2400
performance. Some things, which are assumed in making the previous
tables, include the following:
Clock Ratios and Operating Frequencies
Performance is based on the appropriate clock ratio and corresponding
operating frequency:
PPC60x Originated
❏ Count represents number of PPC60x bus clock cycles.
❏ Assumes write posting FIFO is initially empty.
❏ Does not include time taken to obtain grant for PPC60x bus. The
count starts on the same clock period that TS_ is asserted.
❏ PPC60x bus is idle at the time of the start of the transaction. (that is,
no pipelining effects).
❏ Cache aligned transfer, not critical word first.
❏ PCI medium responder with no zero states.
❏ One clock request/one clock grant PCI arbitration.
❏ Write posting enabled.
Table 3-7. Clock Ratios and Operating Frequencies
Ratio
PPC60x
Clock
(MHz)
PCI Clock
(MHz)
SDRAM
Speed
(ns)
5:2 83 33 8
3:2 100 66 8
3:1 100 33 8
2:1 66 33 10
1:1 66 66 10