Motorola MVME2400 Series - Page 66

3-14 Computer Group Literature Center Web Site
Functional Description
3
Notes
1. SDRAM speed attributes are programmed for the following:
CAS_latency = 2, tRCD = 2 CLK Periods, tRP = 2 CLK Periods,
tRAS = 5 CLK Periods, tRC = 7 CLK Periods, tDP = 2 CLK
Periods, and the swr_dpl bit is set in the SDRAM Speed Attributes
Register.
4-Beat Write after 4-Beat Write,
SDRAM Bank Active - Page Hit
3-1-1-1 3-1-1-1 for the second burst
write after idle.
2-1-1-1 for subsequent burst
writes.
1-Beat Read after idle,
SDRAM Bank Inactive
10
1-Beat Read after idle,
SDRAM Bank Active - Page Miss
12
1-Beat Read after idle,
SDRAM Bank Active - Page Hit
7
1-Beat Read after 1-Beat Read,
SDRAM Bank Active - Page Miss
8
1-Beat Read after 1-Beat Read,
SDRAM Bank Active - Page Hit
5
1-Beat Write after idle,
SDRAM Bank Active or Inactive
5
1-Beat Write after 1-Beat Write,
SDRAM Bank Active - Page Miss
13
1-Beat Write after 1-Beat Write,
SDRAM Bank Active - Page Hit
8
Table 3-8. 60x Bus to SDRAM Access Timing (100 MHz/PC100 SDRAMs)
ACCESS TYPE
Access Time
(tB1-tB2-tB3-tB4)
Comments