Motorola MVME2400 Series - Figure 3-2. Timing Definitions for PPC Bus to SDRAM Access

Block Diagram
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2. The Hawk is configured for “no external registers” on the SDRAM
control signals.
3. tB1, tB2, tB3, and tB4 are specified in the following figure.
Figure 3-2. Timing Definitions for PPC Bus to SDRAM Access
Notes
1. When the initial bus state is idle, tB1 reflects the number of CLK
periods from the rising edge of the CLK that drives TS_low, to the
rising edge of the CLK that samples the first TA_low.
2. When the bus is busy and TS_ is being asserted as soon as possible
after Hawk asserts AACK_ the back-to-back condition occurs.
When back-to-back cycles occur, tB1 reflects the number of CLK
periods from the rising edge of the CLK that samples the last TA_
tB1(From Idle) tB1(Back-to-Back)
tB2
tB3
tB4