Block Diagram
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3
❏ Updating firmware ROM
Under normal operation, the Flash devices are in “read-only” mode, their
contents are pre-defined, and they are protected against inadvertent writes
due to loss of power conditions. However, for programming purposes,
programming voltage is always supplied to the devices and the Flash
contents may be modified by executing the proper program command
sequence. Refer to the PFLASH command in the PPCbug Debugging
Package User’s Manual for further device-specific information on
modifying Flash contents.
ROM/Flash Performance
The SMC provides the interface for two blocks of ROM/Flash. Access
times to ROM/Flash are programmable for each block. Access times are
also affected by block width. The following tables in this subsection show
access times for ROM/Flash when configured for different device access
times.
Note The information in Table 3-9 is appropriate when configured
with devices with an access time equal to 12 CLK periods.
Table 3-9. PPC Bus to ROM/Flash Access Timing (120ns @ 100 MHz)
ACCESS TYPE
CLOCK PERIODS REQUIRED FOR:
Total
Clocks
1st Beat 2nd Beat 3rd Beat 4th Beat
16
Bits
64
Bits
16
Bits
64
Bits
16
Bits
64
Bits
16
Bits
64
Bits
16
Bits
64
Bits
4-Beat Read 70 22 64 16 64 16 64 16 262 70
4-Beat Write N/A N/A
1-Beat Read (1 byte) 2222------2222
1-Beat Read (2 to 8 bytes)7022------7022
1-Beat Write 2121------2121
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