Motorola MVME2400 Series - CHAPTER 4 Programming Details; Introduction; Memory Maps

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4Programming Details
Introduction
This chapter provides information useful in programming the
MVME240x. This includes a description of memory maps, control and
status registers, PCI arbitration, interrupt handling, sources of reset, and
big/little-endian issues.
For additional programming information about the MVME240x, refer to
the MVME2400 Series VME Processor Module Programmer’s Reference
Guide, listed in Appendix D, Related Documentation.
For programming information about the PMCs, refer to the applicable
user’s manual furnished with the PMCs.
Memory Maps
There are multiple buses on the MVME240x and each bus domain has its
own view of the memory map. The following sections describe the
MVME240x memory organization from the following three points of
view:
❏ The mapping of all resources as viewed by the MPU (processor bus
memory map)
❏ The mapping of onboard resources as viewed by PCI local bus
masters (PCI bus memory map)
❏ The mapping of onboard resources as viewed by VMEbus masters
(VMEbus memory map)
Additional, more detailed memory maps can be found in the MVME2400
Series VME Processor Module Programmer’s Reference Guide.