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• Negative Flag (N) - Bit 7 of a byte represents the sign of that byte, with 0 being positive
and 1 being negative. The negative flag (also known as the sign flag) is set if this sign bit
is 1.
The flags are arranged in the status register in the order shown in figure 2-3. Bit 5 of the
status register is unused.
Figure 2-4. Status register layout.
2.4 Interrupts
Interrupts prevent the standard sequential execution of code and cause the processor to
attend to the interrupt. Interrupts are usually generated by hardware which requires attention,
but can be triggered by software. The NES has three different types of interrupt, NMI, IRQ
and reset. The addresses to jump to when an interrupt occurs are stored in a vector table in
the program code at $FFFA-$FFFF. When an interrupt occurs the system performs the
following actions [30]:
1. Recognize interrupt request has occurred.
2. Complete execution of the current instruction.
3. Push the program counter and status register on to the stack.
4. Set the interrupt disable flag to prevent further interrupts.
5. Load the address of the interrupt handling routine from the vector table into the program
counter.
6. Execute the interrupt handling routine.
7. After executing a RTI (Return From Interrupt) instruction, pull the program counter and
status register values from the stack.
8. Resume execution of the program.
IRQs, or maskable interrupts, are generated by certain memory mappers. They are ignored
by the processor if the interrupt disable flag is set. IRQs can be triggered by the software by
use of the BRK (Break) instruction. When an IRQ occurs the system jumps to the address
located at $FFFE and $FFFF.
NMI (Non-Maskable Interrupt) is the type of interrupt generated by the PPU when V-Blank
occurs at the end of each frame. NMIs are not affected by the interrupt disable bit in the
status register, so execution is always interrupted when they occur [31]. However, triggering
of a NMI can be prevented if bit 7 of PPU Control Register 1 ($2000) is clear. When a NMI
occurs the system jumps to the address located at $FFFA and $FFFB. The handling of NMIs
is shown in figure 2-4.
Reset interrupts are triggered when the system first starts and when the user presses the
reset button. When a reset occurs the system jumps to the address located at $FFFC and
$FFFD.
The system gives the highest priority to reset requests, followed by NMI and finally IRQ [7].
The NES has an interrupt latency of 7 cycles, which means it takes 7 CPU cycles to begin
executing the interrupt handler.
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