1508(RM-388)
Baseband Description and Troubleshooting
Nokia Customer
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Issue 1
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VDD_DIG 3V 250mA
Always enabled except during power-off
mode
VDD_CORE 1.8V 150mA
Enabled only when the system is powered
on (Off during sleep and power-off modes)
VDD_TXPLL 3.0V 80mA Enabled only when the transmitter is on
VDD_TXXO 2.8V 80mA
Enabled only when the system is powered
on (Off during sleep and power-off modes)
KEYPAD_LED 2.8V 100mA
Enabled when the system is powered on, or
the keys are pressed, etc.
VDD_RX 2.85V 80mA Enabled when the receiver is on
VDD_TX 2.85V 150mA Enabled when the transmitter is on
VDD_VIBE 3.0V 150mA
Enabled only when the system is powered
on (Off during sleep and power-off modes)
VC-TCXO
The CBP device integrates a phase-locked loop from the TCXO clock input.
The PMU optimizes TCXO operation that enables and disables appropriate circuits in
the proper sequence. The controller is enabled by the OSC_EN signal from the CBP.
When the selected transition occurs at OSC_EN, the controller quickly enables the
TCXO regulator and the input buffer, and begins counting SLEEP_CLK pulses.
Within an initial power on period, the TCXO will be stabilized to its own calibrated
frequency. This initial period, in units of 32.768 kHz clock pulses, is programmed into
a timer within the controller. When the timer expires, the output buffer is enabled. It
synchronizes with the TCXO input such that the TCXO_OUT signal is glitch free, only
valid TCXO pulses are output.
SLEEP Crystal Circuit for 32.768 kHz
The 32.768 kHz crystal oscillator is the primary SLEEP clock source when TCXO
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