The next block is a programmable gain amplifier (PGA), which has the second DC-offset compensation block
around it. The DC-offset compensation method is again based on digital successive approximation technique.
The last block in the analog receiver is an output buffer amplifier, which feeds the differential I/Q signals off-
chip to be A/D converted in the digital baseband.
VCXO and PLL
The VCO frequency is locked by a PLL (phase locked loop) into a stable frequency source given by a VCXO. The
frequency of the VCXO is in turn locked into the frequency of the base station with the help of an AFC (automatic
frequency control) voltage, which is generated in the UEM. The reference frequency is 26 MHz.
The VCXO also provides a 26 MHz system clock for the digital baseband.
The PLL is located in PMB3258 and it is controlled via the RFBUS.
RM-258; RM-259
System Module
Issue 1 COMPANY CONFIDENTIAL Page 6 –23
Copyright © 2007 Nokia. All rights reserved.
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