Basic System Configuration Guide System Management
Edition: 01 3HE 11010 AAAC TQZZA 217
6.4 Node Timing
The 7705 SAR supports a centralized synchronization system with an SSU in each
CSM. The SSU can be synchronized to a traceable primary reference clock through
an external timing port, line interface, or timing-over-packet technology. The transmit
clock of each T1/E1, DS3/E3, SONET/SDH port or synchronous Ethernet-capable
port (referred to as a synchronous Ethernet port in this guide) can then be configured
to use the node clock or alternatives.
The 7705 SAR supports three timing references — one external and two internal.
The timing references can be configured as an ordered list of highest to lowest
priority. The system uses an available valid timing reference with the highest priority.
If a failure on the current timing reference occurs, the next highest timing reference
takes over. The reference switching can be configured to operate in a revertive or
non-revertive manner with the sync-if-timing revert command. Revertive switching
always selects the highest-priority valid timing reference as the current source. If a
reference with a higher priority becomes valid, the system automatically switches to
that timing reference. Non-revertive switching means that the active timing reference
remains selected while it is valid, even if a higher-priority timing reference becomes
available. If the current timing reference becomes invalid, then a switch to the
highest-priority available timing reference is initiated. If all the timing references fail
or have not been configured, the SSU enters holdover mode of its Stratum 3
oscillator (if it was previously synchronized) or free-run mode.
The external timing reference input with a 2.048 MHz G.703 signal, 5 or 10 MHz sine
wave, is available directly on the following:
• 7705 SAR-M (all variants)
• 7705 SAR-H
• 7705 SAR-Hc
• 7705 SAR-A (all variants)
• 7705 SAR-Ax
• 7705 SAR-X
The 7705 SAR-8 CSMv2 does not support a 5 MHz signal. On the 7705 SAR-18, the
external timing reference input with a 2.048 MHz G.703, T1 (100 Ω), or E1 (120 Ω),
is supported by the BITS ports 1 and 2 located on the Alarm module.
The two internal timing references originate from timing extracted from interface
ports. This timing can be recovered directly from physical layer framing on a T1/E1
port, from adaptive timing recovery for TDM pseudowires, or from a synchronous
Ethernet port.
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