7 Additional information
BU 0630 en-2020 53
Pos: 32 3 /Anlei tung en/El ektr onik/S afety /8. Zus atzin form ationen /6. Si cherh eitss chaltg erät e/OS SD-Ausg äng e, T est puls e [ SK 5 00P ] @ 40\m od_1578901672922_388.docx @ 2582790 @ 3 @ 1
7.1.3 OSSD outputs, test pulses
The OSSD signal must satisfy the following requirements:
• D ≥ 90 % (duty, switch-on ratio)
The supply voltage is applied for at least 90% of the time
Example: After a test pulse with duration t
OSSD
the supply voltage is connected for at least 9*t
OSSD
.
• Double pulses are permissible if the two pulses are at least 2 * t
OSSD
apart and the condition for D is
fulfilled.
Permissible test pulses for an OSSD
Example
1. First test pulse with width t
OSSD
.
2. The supply voltage is present for at least 1 * t
OSSD
.
3. Second test pulse with width t
OSSD
.
4. The supply voltage is present for at least 17 * t
OSSD
.
• The width of the test pulse should be within the range 0.2 ms ≤ t
OSSD
≤ 0.5 ms. The maximum width
of the test pulse depends on the application class:
OSSD,max
Depending on the application class and the length of the test pulse, it may be necessary to increase
the minimum input voltage V
IS_24V,min
.
Voltage correction of long OSSD test pulses
This voltage correction is cumulative with other corrections.
Voltage correction of long OSSD test pulses