Novatek NT6862-5 Series - User Manual

NT6862-5xxxx
8-Bit Microcontroller for Monitor
1 V2.2
Features
n Operating voltage range: 4.5V to 5.5V
n CMOS technology for low power consumption
n 6502 8-bit CMOS CPU core
n 8 MHz operation frequency
n 32K/24K/16K bytes of ROM
n 512 bytes of RAM
n One 8-bit base timer
n 13 channels of 8-bit PWM outputs with 5V open drain
n 4 channel A/D converters with 6-bit resolution
n 25 bi-directional I/O port pins (8 dedicated I/O pins)
n Hsync/Vsync signals processor for separate &
composite signals which includes hardware sync
signals polarity detection and frequency counters with
2 sets of Hsync counting intervals
n Hsync/Vsync polarity controlled output, 5 selectable
free run output signals and self-test patterns, auto-
mute function, half freq. I/O function
n Add a jitter filter at the front end of Hsync input path,
reduce the jitter interference of Hysync input
n Two built-in I
2
C bus interfaces support VESA
DDC1/2B+
n Two layers of interrupt management
NMI interrupt sources
- INTE0 (External INT with selectable edge trigger)
- INTMUTE (Auto Mute Activated)
IRQ interrupt sources
- INTS0/1 (SCL Go-low INT)
- INTA0/1 (Slave Address Matched INT)
- INTTX0/1 (Shift Register INT)
- INTRX0/1 (Shift Register INT)
- INTNAK0/1 (No Acknowledge)
- INTSTOP0/1 (Stop Condition Occurred INT)
- INTE1 (External INT with Selectable Edge Trigger)
- INTV (VSYNC INT)
- INTMR (Base Timer INT)
- INTADC (AD Conversion Done INT)
n Hardware Watch-dog timer function
n 40-pin P-DIP and 42-pin S-DIP packages
General Description
The NT6862 is a new generation monitor µC for auto-sync
and digital control applications. Particularly, this chip
supports various and efficient functions to allow users to
easily develop USB monitors. It contains the 6502 8-bit
CPU core, 512 bytes of RAM used as working RAM and
stack area, 32K bytes of OTP ROM, 13-channels of 8-bit
PWM D/A converters, 4-channel A/D converters for key
detection which save I/O pins, one 8-bit pre-loadable base
timer, internal Hsync and Vsync signals processor, a
Watch-dog timer which prevents the system from abnormal
operation, and two I
2
C bus interfaces. The user can store
EDID data in the 128 bytes of RAM for DDC1/2B, so that
user can reduce a dedicated EEPROM for EDID. A Half
frequency output function can save external one-shot
circuit. These designs are committed to reduce component
cost. The 42 pin S-DIP IC provides two additional I/O pins –
port40 & port41, Part number NT6862U represents the S-
DIP IC. For future reference, port40 & port42 are only
available for the 42 pin S-DIP IC.

Summary

Pin Configurations

40-Pin P-DIP

Details the pin assignments and functions for the 40-pin P-DIP package.

42-Pin S-DIP

Details the pin assignments and functions for the 42-pin S-DIP package.

11. Interrupt Controller

Nonmaskable Interrupt Group

Details the NMI group interrupt sources, including INTE0 and INTMUTE.

Maskable Interrupt Group

Details the IRQ group interrupt sources, including INTADC, INTV, INTE1, and INTMR.

DDC Channel 0;1 Maskable Interrupt Sources

Lists specific interrupt sources for DDC channels 0 and 1.

12. I;O PORTS

12.1. PORTO: P00-P07

Describes the 8-bit bi-directional I/O port PORTO, including its features and pin assignments.

12.2. Port1: P10 - P16

Details the 7-bit bi-directional I/O port PORT1, its features, and pin assignments.

12.3. PORT2: P20 - P27

Describes the 8-bit bi-directional I/O port PORT2, its programming, and pull-up resistors.

12.4. PORT3: P30 - P31

Details the 2-bit bi-directional open-drain I/O port PORT3, its configuration and use.

12.5. PORT4: P40 - P41

Describes the 2-bit bi-directional I/O port PORT4, available on 42pin SDIP IC.

13. H;V Sync Signals Processor

13.1. V & H Counter Register: VCNTL;H, HCNTL;H

Details the Vsync and Hsync counter registers and their operation.

13.2. Sync Processor Control Register

Explains control registers for sync processing, including polarity and free run settings.

13.3 Power Saving Mode detect

Describes power saving modes (Normal, Stand-by, Suspend, Off) for video.

15. I²C Bus Interface: DDC1 & DDC2 B Slave Mode

15.1. DDC1 bus interface

Details the DDC1 mode of I2C bus, using Vsync as clock and SDA for data output.

15.2. DDC2 B + Slave & Master Mode Bus Interface

Describes DDC2B+ mode, covering SLAVE and MASTER operations.

15.3. DDC2 B Slave Mode Bus Interface

Details DDC2B slave mode operation, including start/stop conditions and address matching.

15.4 DDC2 B+ Master Mode Bus Interface

Details DDC2B+ master mode operation, including SCL clock generation and data transfer.

Package Information

P-DIP 40 L Outline Dimensions

Provides dimension details for the 40-lead Plastic Dual In-line Package (P-DIP).

S-DIP 42 L Outline Dimensions

Provides dimension details for the 42-lead Shrink Dual In-line Package (S-DIP).

Novatek NT6862-5 Series Specifications