Supported Interfaces
This section describes the DPU Controller supported interfaces. Each numbered interface
referenced in the figures is described in the following table with a link to detailed
information.
FHHL DPU Controller Layout and Interface Information
OPN DPU Controller Component Side DPU Controller Print Side
900-9D3C6-
00CV-GA0
900-9D3C6-
00CV-DA0
Ite
m
Interface Description
1
System-
on-Chip
(SoC)
16 Arm-Cores SoC
2 Networkin
g Interface
The network traffic is transmitted through the DPU Controller
QSFP112 connectors. The QSFP112 connectors allow the use of
Note
The below figures are for illustration purposes only and might not
reflect the current revision of the DPU Controller.
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