The register maps of the peripherals are located on 4-KB boundaries. Each peripheral is
allocated one or more 4-KB block(s) of the memory map. Two global external module
enables are available for the remaining address space to allow for customization and
expansion of addressed peripheral devices.
20.2 Memory map/register definition
The AIPS module(s) on this device do(es) not contain any user-programmable registers.
20.3
Functional description
The peripheral bridge functions as a bus protocol translator between the crossbar switch
and the slave peripheral bus.
The peripheral bridge manages all transactions destined for the attached slave devices and
generates select signals for modules on the peripheral bus by decoding accesses within
the attached address space.
20.3.1
Access support
Aligned and misaligned 32-bit, 16-bit, and byte accesses are supported for 32-bit
peripherals. Misaligned accesses are supported to allow memory to be placed on the slave
peripheral bus. Peripheral registers must not be misaligned, although no explicit checking
is performed by the peripheral bridge. All accesses are performed with a single transfer.
All accesses to the peripheral slots must be sized less than or equal to the designated
peripheral slot size. If an access is attempted that is larger than the targeted port, an error
response is generated.
Memory map/register definition
K22F Sub-Family Reference Manual, Rev. 4, 08/2016
412 NXP Semiconductors
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