NXP Semiconductors K22F series - Page 870

Ch n trigger
PDBCHnDLY0
PDBCHnDLYm
=
Ack 0
Pre-trigger 0
Ch n pre-trigger 0
Ch n pre-trigger m
=
BB[m], TOS[m]
BB[0], TOS[0]
EN[0]
EN[m]
MULT
Ack m
Pre-trigger m
Trigger-In 0
Sequence Error
Detection
ERR[M - 1:0]
PRESCALER
PDBCNT
PDBMOD
=
CONT
Trigger-In 1
Trigger-In 14
SWTRIG
TRIGSEL
DACINTx
EXTx
=
PDBIDLY
=
PDB interrupt
TOEx
=
=
POyDLY2
POyDLY1
Pulse
Generation
Pulse-Out y
PDBPOEN[y]
Pulse-Out y
DAC interval
trigger x
From trigger mux
TOEx
DAC external
trigger input
Control
logic
PDB counter
DAC interval
counter x
Figure 38-1. PDB block diagram
In this diagram, only one PDB channel n, one DAC interval trigger x, and one Pulse-Out
y are shown. The PDB-enabled control logic and the sequence error interrupt logic are
not shown.
Introduction
K22F Sub-Family Reference Manual, Rev. 4, 08/2016
870 NXP Semiconductors