FTFA_FOPT [4,0] Core/system clock Bus/Flash clock Description
00 0x7 (divide by 8) 0x1 (divide by 2) Low power boot
01 0x3 (divide by 4) 0x1 (divide by 2) Low power boot
10 0x1 (divide by 2) 0x1 (divide by 2) Low power boot
11 0x0 (divide by 1) 0x1 (divide by 2) Fast clock boot
This gives the user flexibility in selecting between a lower frequency, low-power boot
option vs. higher frequency, higher power during and after reset.
The flash erased state defaults to fast clocking mode, since these bits reside in flash,
which is logic 1 in the flash erased state. To enable a lower power boot option, program
the appropriate bits in FTFA_FOPT. During the reset sequence, if either of the control
bits is cleared, the system is in a slower clock configuration. Upon any system reset, the
clock dividers return to this configurable reset state.
5.5.2 VLPR mode clocking
The clock dividers cannot be changed while in VLPR mode. They must be programmed
prior to entering VLPR mode to guarantee operation. Max frequency limitations for
VLPR mode is as follows :
• the core/system clocks are less than or equal to 4 MHz, and
• the bus and flash clocks are less than or equal to 1 MHz
NOTE
When the MCG is in BLPI and clocking is derived from the
Fast IRC, the clock divider controls (MCG_SC[FCRDIV],
SIM_CLKDIV1[OUTDIV1], and SIM_CLKDIV1[OUTDIV4])
must be programmed such that the resulting flash clock nominal
frequency is 800 kHz or less. In this case, one example of
correct configuration is MCG_SC[FCRDIV]=000b,
SIM_CLKDIV1[OUTDIV1]=0000b and
SIM_CLKDIV1[OUTDIV4]=100b, resulting in a divide by 5
setting.
Internal clocking requirements
KL25 Sub-Family Reference Manual, Rev. 3, September 2012
120 Freescale Semiconductor, Inc.
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