NXP Semiconductors KL25 Series - LLWU Pin Enable 2 Register (LLWU_PE2)

LLWU_PE1 field descriptions (continued)
Field Description
00 External input pin disabled as wakeup input
01 External input pin enabled with rising edge detection
10 External input pin enabled with falling edge detection
11 External input pin enabled with any change detection
3–2
WUPE1
Wakeup Pin Enable For LLWU_P1
Enables and configures the edge detection for the wakeup pin.
00 External input pin disabled as wakeup input
01 External input pin enabled with rising edge detection
10 External input pin enabled with falling edge detection
11 External input pin enabled with any change detection
1–0
WUPE0
Wakeup Pin Enable For LLWU_P0
Enables and configures the edge detection for the wakeup pin.
00 External input pin disabled as wakeup input
01 External input pin enabled with rising edge detection
10 External input pin enabled with falling edge detection
11 External input pin enabled with any change detection
15.3.2 LLWU Pin Enable 2 register (LLWU_PE2)
LLWU_PE2 contains the field to enable and select the edge detect type for the external
wakeup input pins LLWU_P7-LLWU_P4.
NOTE
This register is reset on Chip Reset not VLLS and by reset
types that trigger Chip Reset not VLLS. It is unaffected by reset
types that do not trigger Chip Reset not VLLS. See the
Introduction details for more information.
Address: 4007_C000h base + 1h offset = 4007_C001h
Bit 7 6 5 4 3 2 1 0
Read
WUPE7 WUPE6 WUPE5 WUPE4
Write
Reset
0 0 0 0 0 0 0 0
LLWU_PE2 field descriptions
Field Description
7–6
WUPE7
Wakeup Pin Enable For LLWU_P7
Enables and configures the edge detection for the wakeup pin.
00 External input pin disabled as wakeup input
01 External input pin enabled with rising edge detection
Table continues on the next page...
Memory map/register definition
KL25 Sub-Family Reference Manual, Rev. 3, September 2012
250 Freescale Semiconductor, Inc.