NXP Semiconductors KL25 Series - Page 30

Section number Title Page
39.3.2 Transmitter functional description...............................................................................................................738
39.3.3 Receiver functional description...................................................................................................................740
39.3.4 Additional UART functions.........................................................................................................................743
39.3.5 Interrupts and status flags............................................................................................................................745
Chapter 40
Universal Asynchronous Receiver/Transmitter (UART1 and UART2)
40.1 Introduction...................................................................................................................................................................747
40.1.1 Features........................................................................................................................................................747
40.1.2 Modes of operation......................................................................................................................................747
40.1.3 Block diagram..............................................................................................................................................748
40.2 Register definition.........................................................................................................................................................750
40.2.1 UART Baud Rate Register: High (UARTx_BDH)......................................................................................751
40.2.2 UART Baud Rate Register: Low (UARTx_BDL).......................................................................................751
40.2.3 UART Control Register 1 (UARTx_C1).....................................................................................................752
40.2.4 UART Control Register 2 (UARTx_C2).....................................................................................................753
40.2.5 UART Status Register 1 (UARTx_S1)........................................................................................................755
40.2.6 UART Status Register 2 (UARTx_S2)........................................................................................................756
40.2.7 UART Control Register 3 (UARTx_C3).....................................................................................................758
40.2.8 UART Data Register (UARTx_D)...............................................................................................................760
40.2.9 UART Control Register 4 (UARTx_C4).....................................................................................................760
40.3 Functional description...................................................................................................................................................761
40.3.1 Baud rate generation....................................................................................................................................761
40.3.2 Transmitter functional description...............................................................................................................762
40.3.3 Receiver functional description...................................................................................................................764
40.3.4 Interrupts and status flags............................................................................................................................767
40.3.5 DMA Operation...........................................................................................................................................768
KL25 Sub-Family Reference Manual, Rev. 3, September 2012
30 Freescale Semiconductor, Inc.