23.4 Functional Description
In the following discussion, the term DMA request implies that DCRn[START] is set, or
DCRn[ERQ] is set and then followed by assertion of the properly selected DMA
peripheral request. The START bit is cleared when the channel is activated.
Before initiating a dual-address access, the DMA module verifies that DCRn[SSIZE] and
DCRn[DSIZE] are consistent with the source and destination addresses. If they are not
consistent, the configuration error bit, DSRn[CE], is set. If misalignment is detected, no
transfer occurs, DSRn[CE] is set, and, depending on the DCR configuration, an interrupt
event may be issued. If the auto-align bit, DCRn[AA], is set, error checking is performed
on the appropriate registers.
A read/write transfer sequence reads data from the source address and writes it to the
destination address. The number of bytes transferred is the largest of the sizes specified
by DCRn[SSIZE] and DCRn[DSIZE] in the DMA Control Registers (DCRn).
Source and destination address registers (SARn and DARn) can be programmed in the
DCRn to increment at the completion of a successful transfer.
23.4.1 Transfer Requests (Cycle-Steal and Continuous Modes)
The DMA channel supports software-initiated or peripheral-initiated requests. A request
is issued by setting DCRn[START] or when the selected peripheral request asserts and
DCRn[ERQ] is set. Setting DCRn[ERQ] enables recognition of the peripheral DMA
requests. Selecting between cycle-steal and continuous modes minimizes bus usage for
either type of request.
• Cycle-steal mode (DCRn[CS] = 1)—Only one complete transfer from source to
destination occurs for each request. If DCRn[ERQ] is set, the request is peripheral
initiated. A software-initiated request is enabled by setting DCRn[START].
• Continuous mode (DCRn[CS] = 0)—After a software-initiated or peripheral request,
the DMA continuously transfers data until BCRn reaches zero. The DMA performs
the specified number of transfers, then retires the channel.
In either mode, the crossbar switch performs independent arbitration on each slave port
after each transaction.
Chapter 23 DMA Controller Module
KL25 Sub-Family Reference Manual, Rev. 3, September 2012
Freescale Semiconductor, Inc. 361
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