MCG_C6 field descriptions (continued)
Field Description
any Stop mode. Otherwise, a reset request may occur while in Stop mode. CME0 should also be set to a
logic 0 before entering VLPR or VLPW power modes if the MCG is in BLPE mode.
0 External clock monitor is disabled for OSC0.
1 External clock monitor is enabled for OSC0.
4–0
VDIV0
VCO 0 Divider
Selects the amount to divide the VCO output of the PLL. The VDIV 0 bits establish the multiplication factor
(M) applied to the reference clock frequency. After the PLL is enabled (by setting either PLLCLKEN 0 or
PLLS), the VDIV 0 value must not be changed when LOCK 0 is zero.
Table 24-9. PLL VCO Divide Factor
VDIV 0 Multiply
Factor
VDIV 0 Multiply
Factor
VDIV 0 Multiply
Factor
VDIV 0 Multiply
Factor
00000 24 01000 32 10000 40 11000 48
00001 25 01001 33 10001 41 11001 49
00010 26 01010 34 10010 42 11010 50
00011 27 01011 35 10011 43 11011 51
00100 28 01100 36 10100 44 11100 52
00101 29 01101 37 10101 45 11101 53
00110 30 01110 38 10110 46 11110 54
00111 31 01111 39 10111 47 11111 55
24.3.7 MCG Status Register (MCG_S)
Address: 4006_4000h base + 6h offset = 4006_4006h
Bit 7 6 5 4 3 2 1 0
Read LOLS LOCK0 PLLST IREFST CLKST OSCINIT0 IRCST
Write
Reset
0 0 0 1 0 0 0 0
MCG_S field descriptions
Field Description
7
LOLS
Loss of Lock Status
This bit is a sticky bit indicating the lock status for the PLL. LOLS is set if after acquiring lock, the PLL
output frequency has fallen outside the lock exit frequency tolerance, D
unl
. LOLIE determines whether an
interrupt request is made when LOLS is set. LOLRE determines whether a reset request is made when
LOLS is set. This bit is cleared by reset or by writing a logic 1 to it when set. Writing a logic 0 to this bit has
no effect.
Table continues on the next page...
Memory Map/Register Definition
KL25 Sub-Family Reference Manual, Rev. 3, September 2012
378 Freescale Semiconductor, Inc.
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