NXP Semiconductors KL25 Series - Page 49

ARM Cortex-M0+
Core
Debug Interrupts
Crossbar
switch
Figure 3-1. Core configuration
Table 3-3. Reference links to related information
Topic Related module Reference
Full description ARM Cortex-M0+ core,
r0p0
ARM Cortex-M0+ Technical Reference Manual, r0p0
System memory map System memory map
Clocking Clock distribution
Power management Power management
System/instruction/data
bus module
Crossbar switch Crossbar switch
Debug Serial Wire Debug
(SWD)
Debug
Interrupts Nested Vectored
Interrupt Controller
(NVIC)
NVIC
Miscellaneous Control
Module (MCM)
MCM
3.3.1.1 ARM Cortex M0+ Core
The ARM Cortex M0+ parameter settings are as follows:
Table 3-4. Table 3. ARM Cortex-M0+ parameter settings
Parameter Verilog Name Value Description
Arch Clock Gating ACG 1 = Present Implements architectural clock
gating
DAP Slave Port Support AHBSLV 1 Support any AHB debug
access port (like the CM4
DAP)
DAP ROM Table Base BASEADDR 0xF000_2003 Base address for DAP ROM
table
Table continues on the next page...
Chapter 3 Chip Configuration
KL25 Sub-Family Reference Manual, Rev. 3, September 2012
Freescale Semiconductor, Inc. 49